Ultra Low Power Clock Generator for Heartrate Monitoring System

Abstract

An efficient clock multiplier circuit is presented which supplies an LED driver with a 2MHz clock based on a 32kHz reference. This circuit is a key part of an ultra-low power heart rate monitoring system based on pulse oximetry. A novel aspect of the clock multiplier is that it has a highly digital implementation based on a frequency locked loop (FLL) architecture which allows operation at 0.5V supply voltage with less than 10 microAmps of current consumption. Also, the design is robust in the presence of process, temperature, and supply voltage variations while avoiding complex calibration or analog circuits such as bandgap voltage references. This talk will present the overall architecture of the clock multiplier as well key circuit blocks such as a digitally-controlled oscillator. Design challenges will be discussed along with circuit solutions and simulation results that verify target operation and performance of the system. Finally, a layout of the custom IC implementing the clock multiplier is presented along with system level simulations confirming its functionality.

Date of Award	2012
Original language	American English
Supervisor	Michael Perrott (Supervisor)