Switched Capacitor Based DC-DC Converter Design with Applications in Power Efficiency and Security Primitives

Abstract

Energy efficiency constitutes a foundational constraint in current system-on-chip (SoC) devices. Enhanced energy efficiency yields prolonged device lifespan and heightened operational efficacy. Consequently, a power management unit (PMU) is imperative, especially in scenarios necessitating swift responses to workload fluctuations. Moreover, the pursuit of heterogeneous integration, aimed at optimizing performance while minimizing energy consumption, underscores the indispensability of PMUs. Presently, most SoC devices incorporate PMUs featuring voltage regulators, be it linear or switching type, tasked with voltage regulation and power switching. This research focuses on switched-capacitor DC-DC (SC-DCDC) converters, a class of switching type regulators that enable full integration and achieve commendable efficiency levels, particularly at high conversion ratios. The proposed design, implemented in 22-nm FD-SOI process technology, operates across a voltage range of 0.4–0.8V and supports up to 100mA in bypass mode, achieving a peak efficiency of 98.8%.
This research further explores and advances methodologies for efficient power management, addressing critical challenges in modern integrated systems. The proposed design emphasizes the development of a coarse-fine voltage regulation strategy, complemented by adaptive voltage regulation. This approach is tailored to mitigate the detrimental impacts of process, voltage, and temperature (PVT) variations, as well as aging degradation, thereby ensuring sustained performance and reliability over time. There is a critical need to operate at the optimal energy point, accounting for silicon performance variations to achieve maximum efficiency. By leveraging reduced timing slack in nominal conditions, this methodology optimizes energy efficiency while maintaining performance integrity. In the system under test, this approach resulted in an average power reduction of approximately 34%, highlighting its effectiveness in balancing efficiency and reliability.
Beyond power efficiency, the research also broadens its scope to address security-enhancement objectives. To this end, the integration of a SC-DCDC converter with a Physical Unclonable Function (PUF) is implemented. This integration not only improves power efficiency but also strengthens the security framework, making the system more resilient to adversarial attacks and modeling threats. The proposed system has been implemented using 22-nm FDSOI process technology, with statistical analyses performed based on silicon measurements. Experimental results indicate that the proposed design achieves a significant improvement of approximately 31% in diffuseness compared to the baseline PUF architecture, while maintaining a consistent level of uniformity. Additionally, the system demonstrates enhanced robustness against machine learning-based modeling attacks, achieving a notable 25.48% reduction in prediction accuracy. These findings underscore the effectiveness of the proposed enhancements in enhancing both the security and reliability of the system.

Date of Award	7 May 2025
Original language	American English
Supervisor	Baker Mohammad (Supervisor)