Smart FPGA-Based SDR Core for Space Communication

Abstract

Today’s communication systems are modular such that each task required by the communication system for effective data transmission and reception is described by a block that optimizes it. Such an approach has proved to be efficient in describing communication systems. However, the individual optimization of these blocks leads to the sub-optimality of the overall system. In contrast, Deep Learning and Machine Learning concepts ensure the end-to-end optimization of systems through training.

Moreover, CubeSats offer attractive research opportunities due to their low cost and small size. However, CubeSats/Nanosatellites are limited due to the small communication window in which they must transmit their data, the power consumption, size, as well as the limited on-board resources. Therefore, CubeSats throughput must be enhanced, which can be achieved using an SDR implemented on an FPGA.

In this paper, an Autoencoder, which is an Artificial Neural Network, is used to build an FPGA-based communication system that targets CubeSats. This implementation can ensure the global optimization of the system, throughput enhancement, and the ability to reprogram. This is done by considering a High-Level model consisting of a communication system based on the Autoencoders concept that includes a Rician Fading Channel to suit space communication applications. The Encoder, Latent Space/Code, and Decoder of the Autoencoder are equivalent to the communication system’s Transmitter, Channel, and Receiver, respectively. The High-Level model is then trained repeatedly to obtain the hyperparameters that would result in satisfactory validation and training accuracy. The learnable parameters of the network (i.e., weights and biases) are extracted and converted from Floating-Point to Fixed-Point representation. The system’s inference is built using Register Transfer Level (RTL) Modelling to target hardware implementation (e.g., FPGA and ASIC). The simulation results show that the RTL model of the system work as the High-Level model.

Lastly, the RTL Model functionality is verified and synthesized for ASIC and FPGA implementation.

Date of Award	Aug 2023
Original language	American English
Supervisor	HANI Saleh (Supervisor)