Silicon Nanoparticles for Low Power Zinc-Oxide Based Charge Trapping Nano-Memory Devices

  • Nazek El-Atab

Student thesis: Master's Thesis


Current flash memory devices are expected to face two major challenges in the near future: density and voltage scaling. The density of the memory is related to the gate length scaling which is constrained by the gate stack, precisely, the tunnel oxide thickness. In fact, the gate length is required to be adequate with the gate stack in order to maintain a good gate control and to avoid short channel effects. However, in conventional flash memories, the tunnel oxide thickness has a lower limit of 6-8 nm (depending on NOR or NAND structure) in order to avoid back-tunneling and thus leakage of charges which destroys the necessary retention characteristic of the memory (> 10 years). The second problem which needs to be solved is the high program and erase operating voltages. Once again, the limitation to operating voltage scaling is the inability to reduce gate stack thickness. Therefore, it is imperative to find novel structures and materials to be incorporated in the memory cells which would allow tunnel oxide and voltage scaling. In this study, Zinc-Oxide (ZnO) based memory devices are investigated along with the use of 2-nm Silicon nanoparticles (Si NPs) for charge storage. Atomic Layer Deposition was used to deposit the ZnO channel, the blocking oxide, and tunneling oxide. The Si NPs were deposited across the sample by spin-coating. Electrical measurements, the investigation of the energy  band diagram, and the analysis of the threshold voltage shift versus the electric field across the tunnel oxide showed that a large memory window (3.4 V) can be achieved at low operating voltages (1 V) with a good retention of charges (<10 years) when the dominant mechanism of charge emission is the Poole-Frenkel Effect. At higher electric fields, the quantum tunneling mechanism leads. In addition, MOS memory structures are fabricated and studied. Different charge trapping layers were explored: 16-nm InN nanoparticles embedded within ZnO, graphene nanoplatelets, and 2-nm Si NPs. Furthermore, the “Tunnel Band Engineering” (TBE) mechanism is investigated in a simulated Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) memory using Physics Based TCAD. Results show that TBE allows for gate oxide scaling without affecting the retention characteristic of the memory.
Date of AwardMay 2014
Original languageAmerican English
SupervisorAmmar Nayfeh (Supervisor)


  • Silicon Nanoparticles; Zinc Oxide; Nanotubes.

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