Reliable and Efficient Hardware Implementation of PUFs for Secure IoT Applications

Abstract

The distributed nature of the Internet of Things (IoT) and their widespread accessibility make them susceptible to various types of attacks. Consequently, security is a crucial requirement for their deployment. However, the limited computing resources and cost constraints in resource-constrained IoTs often lead to restricted implementation of security functions. Physically Unclonable Functions (PUFs) have emerged as a promising solution for securing IoT systems. Nonetheless, the area utilization and power consumption of PUF architectures are under study for their inclusion in IoTs, especially regarding the requirement of additional blocks to guarantee the reliability and security of PUF keys.

This thesis proposes three efficient hardware architectures of Silicon PUF (SPUF) across different platforms, including Field-Programmable Gate Array (FPGA), Application-Specific Integrated Circuit (ASIC), and Dynamic Random Access Memory (DRAM). Additionally, this research develops Shehana, a key generation unit that utilizes a PUF device, a Temporal Majority Voting (TMV) block, an Error Correction Code (ECC), a Random Number Generator (RNG), and a hash function.

The first proposed design is Algorithmically Optimized Configurable Ring Oscillator PUF (AOCRO), a multi-bit response architecture that reduces the Ring Oscillator (RO) bank size to a single pair of ROs per response bit. AOCRO applies an absorption approach to intermediate responses to enhance entropy and mitigate Machine Learning (ML)-based modeling attacks. Furthermore, AOCRO is developed and analyzed across 50 FPGA boards. Compared with the conventional architectures, AOCRO reduces the area by 67.5% and power consumption by 9.7%.

The kernel-based PUF, the second proposed architecture, utilizes a new extraction approach in Configurable Ring Oscillator (CRO) PUF that exploits the phase shift of the delay elements and the frequency of ROs to generate unique responses. The kernel-based PUF has been implemented in 22nm FDSOI and verified using 8 chips, achieving an area and power reduction of 75% and 65.1%, respectively, compared with the state-of-the-art.

In the third proposed architecture, the DRAM PUF evaluates the delay difference between two adjacent DRAM cells and generates the response through the regular read operation of DRAM. The DRAM PUF has slightly modified the periphery circuitry, which is implemented and verified by SPICE simulation using 65 nm technology. It generates the response within 45µs, which is at least 66.7 times faster than existing systems. Furthermore, the DRAM PUF is also resilient against ML-based modeling attacks, as the prediction accuracy does not exceed 55%.

The aforementioned CRO-based PUF achieved efficient power and area in their implementations. The modified DRAM PUF has minimal area overhead and improves reliability and throughput.

Finally, Shehana, an integrated system, delivers the PUF response with an error rate of 10 7 and secures the generated key by utilizing dynamic helper data and applying ASCON-Hash. Shehana decreases the hardware complexity by utilizing a customized implementation of ECC and lightweight cryptography. In the End-Edge-Cloud paradigm, Shehana has been evaluated for various authentication and key agreement scenarios, including end-to-end, end-to-edge, edge-to-cloud, and end-to-cloud.

Date of Award	16 Dec 2024
Original language	American English
Supervisor	HANI Saleh (Supervisor)