Reconfigurable SRAM-based CAM design for RISC-V implementation

Abstract

This thesis work introduces a reconfigurable SRAM-CAM design for RISC-V implementation that integrates the functionalities of both SRAM and CAM operations. The design offers notable advancements compared to previous CAM models in terms of area, energy, and timing. The proposed SRAM-CAM model enables efficient data access and content-based searching, leveraging the advantages of both SRAM and CAM technologies. One significant feature of the proposed design is the inclusion of a similarity index, which provides valuable information about the number of bit mismatches between the search word and the stored word during CAM search operations. To validate the functionality and performance of the design, extensive simulations and verifications have been conducted using the Cadence platform. These simulations demonstrate the successful integration of SRAM and CAM operations and showcase the improved capabilities offered by the reconfigurable SRAM-CAM design compared to previous CAM models. The proposed design demonstrates notable enhancements over previous CAM designs, including around 20% reduction in area and approximately 25% improvement in energy efficiency. Moreover, the CAM search operations can be performed at a maximum frequency of 1GHz, which represents a doubling of the previous best performance. These advancements contribute to the overall efficiency and performance of the design, making it a significant improvement in the field of CAM technology. While the proposed SRAM-CAM design has been primarily developed for RISC-V implementation, it has the potential to be applied in various other applications beyond the scope of the current study. Exploring the potential of the SRAM-CAM block in HDC applications, where the similarity index feature is essential, could yield valuable results and broaden its range of applications. Overall, the reconfigurable SRAM-CAM design presented in this thesis work demonstrates improved memory capabilities and paves the way for future advancements in memory systems and diverse application domains.

Date of Award	Aug 2023
Original language	American English
Supervisor	Baker Mohammad (Supervisor)