Novel Bipolar Device Technology in 4H-SiC

Abstract

This research is geared towards developing a novel lateral 4H-silicon carbide (SiC) bipolar junction transistor (LBJT) design that not only features optimal performance, but is also much more area-efficient and cost-effective than the conventional 4H-SiC BJT designs. Unlike metal-oxide-semiconductor (MOS) devices, a BJT is well-suited for SiC circuits used at high temperatures (up to 500 °C), due to the absence of a critical gate oxide which makes oxide-reliability a non-issue in BJTs. Digital circuits based on SiC BJTs have a wide range of applications, such as avionics, defense, automobiles, oil exploration, space exploration, and nuclear plants. SiC is an excellent candidate for these applications due to its superior electrical properties such as wide bandgap, low intrinsic carrier concentration, and high thermal conductivity. Despite these merits, the SiC technology has not been widely accepted for digital applications, due to several roadblocks. Unlike the silicon-based complementary MOS (CMOS) technology, where a small-sized, easy to fabricate device has already been standardized for digital applications, no similar efforts have been done in the past to optimize the transistor design currently used in SiC based digital integrated circuits (ICs). In fact, the BJT structure presently used in digital 4H-SiC circuits, is an adaptation of the silicon power BJT, which has a complex fabrication process in addition to large area, low power efficiency, and high cost. This research aims to address these issues by proposing a novel, symmetric, self-aligned, and optimal performance lateral BJT design in 4H-SiC, which is not only much (>90%) smaller in size than the conventional SiC BJTs, but is also easier to fabricate. Furthermore, the optimized LBJT design is modified so that it can be fabricated using the state-of-the-art CMOS process flow, substantially reducing the overall cost and fabrication complexity. Therefore, two LBJT designs are presented in this work- a) a self-aligned optimal performance, and b) a CMOS process compatible design. The optimal performance 4H-SiC LBJT design, with an operating voltage of only 7 V, exhibits a DC current gain of 59 and a cut-off frequency of 1.27 GHz, at room temperature. Whereas, the CMOS process compatible version of the design has a current gain of 51 and a cut-off frequency of 1.03 GHz. Both designs demonstrate stable operation at a wide range of temperatures (27 °C-500 °C). This is the first time that a new bipolar transistor technology, especially designed for 4H-SiC digital logic applications, is proposed. In addition to developing a novel SiC LBJT structure, this work also takes it one step further by designing logic circuits using the optimal performance LBJT design. To achieve this, the SPICE model parameters of the 4H-SiC LBJT are extracted at different temperatures (27 °C, 250 °C and 500 °C). The models are then used to design and optimize an inverter based on the emitter-coupled logic (ECL) technology. The ECL circuit based on the SiC LBJT, which is optimized at a supply voltage of 10 V, exhibits average noise margins of 0.75 V and a propagation delay of 1.07 ns at room temperature, and demonstrates stable operation up to 500 °C. The ECL design is not only the fastest SiC ECL circuit presented to date but also surpasses the speeds of silicon based ECL circuits (~3 ns). The proposed design of the novel SiC LBJT is the first step towards realizing small sized ICs that are well suited for harsh environment applications.

Date of Award	Jun 2017
Original language	American English
Supervisor	Shakti Singh (Supervisor)