Multi-Objective Optimization of 3D Floor-Planning and Placement

  • Puskar Budhathoki

Student thesis: Master's Thesis


Three-Dimensional integrated circuits hold great promise for performance improvement and power savings through the reduction of footprint and average wirelength. However, the technology comes with new challenges especially in the early design stages. One such challenge is the development and use of adequate floorplan representations. Another challenge is thermal management to their productization. Contrasted with the conventional, layerwise 2D floorplanning approaches, genuine 3D layout representations naturally integrate vertical relations between layers. In our research, we present a novel physical design flow that integrates thermaldriven 3D floorplanning with a novel algorithm for thermal TSVs placement that we call localized TSV placement based on native 3D layout data structures. The floorplanning phase accounts for wirelength and chip area while the thermal verification phase uses the insertion of thermal through silicon vias (TSVs) to reduce the number and magnitudes of hot spots. Placement of thermal through-siliconvias (TSVs) has been proposed to improve the vertical heat flow in the chip stack and this alleviate the negative impact of heat dissipation on chip performance and reliability. The essence of the algorithm is to analyze the layered thermal map of the chip stack and then insert thermal TSVs iteratively until the maximal on-chip temperature is below a pre-selected target by accurately determining the location and number of thermal TSVs which has greatest impact in reducing hotspot temperature. The algorithm is implemented within a full flow for thermal-driven 3D floorplanning. The implementation is tested using several standard benchmarks for physical design, and the experimental results show the suitability of our algorithm for significantly reducing maximum chip temperature at reasonable density levels for thermal TSVs (100_ Kelvin reduction at 0.5% TSV density). The impact of thermal TSV insertion strongly increases with the number of chip layers. The larger the die size, the more beneficial the localized placement of thermal TSV's. The presented approach paves the way for thermal-driven design methods that profit from the 3D representations of layouts made of several stacked layers.
Date of Award2014
Original languageAmerican English
SupervisorAndreas Henschel (Supervisor)


  • 3D Floor planning; Thermal TSV; Integrated Circuit; Wirelength; footprint.

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