Modelling and characterizing nano schottky junctions For low power nano devices

Abstract

Complementary Metal-Oxide Semiconductor (CMOS) devices technology is considered essential in most of existing electronic chips and microprocessors. Nowadays, there is a growing interest in scaling down the conventional electronic devices to sub-20 nm scale, to achieve optimum high switching speed and low power consumption. However, scaling down the device size is limited by physical effects inherent in CMOS technology, which results from overlapping of the depletion regions of successive semiconductor junctions. Some other problems also include the gate leakage current, and inability to control dopant distributions on a very small surface area. The new nano device structure, which is developed and patented earlier at Khalifa University and based on reduced M-S contacts using nano metal particles, would help to tackle this issue. The developed approach could help to fabricate low power consumption devices, as electrons transmit through the tunneling process rather than the thermionic process as in conventional CMOS devices. In addition to that, the required operational voltages and currents are considered small. In this work, the characteristics of nano schottky junctions, using numerical and theoretical analyses, are investigated and compared with some available experimental data. Then the analyses are extended to basic devices such as nano transistors and nano integrated logic circuits.

Date of Award	2015
Original language	American English
Supervisor	Moh'D Rezeq (Supervisor)