Memristor-Based In-Memory Computing Architectures and Applications

Abstract

The new era of artificial intelligence (AI), big data and edge computing presents big challenges to both the technology and architecture of conventional computing. At the device level, Silicon-based integrated circuit technologies such as complementary metal-oxidesemiconductor (CMOS) is fast approaching its physical and power limits. While at the architectural level, the von Neumann memory bottleneck is significantly limiting computing throughput. A wide range of emerging memory technologies has been investigated to address those challenges. Resistive random access memory (ReRAM) is a promising technology for building efficient in-memory computing (IMC) architectures due to its ability to perform both storage and computation within same physical device. When these ReRAM-devices are built in a crossbar architecture, they inherently support parallel operations, and can naturally realize a vector-matrix operation with signi?cant savings in energy, area and execution time. Moreover, these devices can be configured to support analog or mixed signal type IMC operations. Furthermore, the low power requirement of ReRAM devices makes them an ideal candidate for resource-constrained Internet-of-Things (IoTs) nodes. The main contribution of this thesis, is the demonstration of the efficient IMC for both analog and digital domains. Three relevant applications have been used to quantify the benefits of the proposed approaches and performance results are compared to state-of-art and traditional implementation. Firstly, a novel memristor-based image compression (MR-IC) architecture that exploits a lossy 2D-Discrete Wavelet Transform (DWT) is proposed. The computational memristor array performs analog IMC on the initially stored transformation coefficients. Analysis of the implementation indicates a 10x reduction in the number of operations when compared to a conventional application-speci?c integrated circuit implementation. This translates to five orders of magnitude reduction in area, 11x improvement in energy efficiency, and 1.28x speedup in computation time with comparable ComplexWavelet Structural Similarity Index (CW-SSIM) for 5-bit image dynamic range. Secondly, two cells have been developed for a new and efficient memristor-based search engine. The first cell is based on a novel stateful heterogeneous memristive XOR gate where both input operands and the output result use memristor devices to store their values. And the second one is based on a voltage-resistance (VR)-XNOR cell, where one operand is represented as voltage and the other as memristance value. Utilizing memristor technology allows for a significantly higher storage density than a conventional CMOS-based technology. The stateful cell was used to build a search engine that is suitable for data stored in memory such as the content-based image retrieval (CBIR). While the VR-XNOR cell is best for search engines with inline matching or learning where one input is coming from a sensor and the other is stored in memory. Moreover, the VR-XNOR cell was also used to form a filter bank architecture that extracts features for convolution neural networks (CNN).

Date of Award	May 2019
Original language	American English