Memristive Stateful Logic Gates for In-Memory Computing Applications

Abstract

Resistive RAM (RRAM) technologies are gaining importance due to their many appealing characteristics, which include non-volatility, small form factor and low power consumption. These characteristics make RRAM highly suited for IoT devices, as well as resource constrained electronic systems. Furthermore, memristive stateful logic circuits, such as the Stateful Material Implication (IMPLY) gate and Memristor Aided Logic (MAGIC) gates, enable in-memory computing based on RRAM crossbar memory structures. This type of memory has the potential to realize high density memory systems with computing capabilities. Therefore, novel memory architectures can be proposed to mitigate the well-known Von Neumann Bottleneck problem, which limits the throughput of the system. This thesis makes contributions to RRAM technology at both the circuit level as well as the architectural level. At the circuit level, the thesis proposes new type of stateful logic circuits that perform 2-input XNOR, 2-input XOR, and n-input NAND functions in two computational steps. Some of the proposed gates hold the output state in input-unlike medium that require additional buffering step for logic cascading. The proposed gates are based on the introduction of design variabilities, such as heterogeneous unipolar/bipolar structures, to perform more complex logic functions (e.g. XNOR) with reduced electrical. At the architectural level, a novel memristive crossbar memory (MCM) architecture with a capability of self-inspection and correction of errors is proposed. This memory architecture utilizes the proposed memristive stateful logic circuits to perform encoding and decoding computations of a particular Hamming code in memristive crossbar memory. The proposed memory architecture supports parallel computations to encode and decode the stored codewords in memory. Therefore, this leads to increase the reliability of the memory system with more efficient computations than the computations of traditional architectures. The functionality of each contribution was simulated in LTspice circuit simulator. In addition, some of the proposed logic circuits were benchmarked by simulation against the state-of-the-art memristor-based logic circuits in terms of latency, area and power consumption.

Date of Award	Jun 2017
Original language	American English
Supervisor	MAHMOUD Al Qutayri (Supervisor)