Low power mm-wave transmitter architecture with on-chip resonator/All digital Phase Locked Loop (PLL)

  • Bahaa Radi

Student thesis: Master's Thesis


Wireless sensor networks have been a research subject in many disciplines. The common building block to all wireless sensor nodes is the wireless transceiver. As lower frequencies, such as the 2.4GHz ISM band, became congested, a need for low power, small size and self-contained (i.e. with no external components) transceivers has become apparent. To address this, a primary focus of this thesis is the design of the transmitter part of the transceiver. The first topic of this thesis is a system level analysis. This system analysis investigates the impact of the form factor of wireless sensor nodes on the optimal RF frequency. The criterion for optimality is selected as the energy efficiency of the entire system including the transmitter and receiver. The conclusion of this analysis supports the choice of 60GHz as the desired frequency for the design of the transmitter. As a second topic of the thesis, two novel ultra-low power (ULP) transmitters are proposed, and the designs are presented. Both transmitters are unconventional in the sense that they have no power amplifiers and Phase-locked loops (PLL) involved. The lack of external crystals is compensated by the existence of an on-chip resonator at the Tx side and a frequency agnostic receiver type. The power amplifier is eliminated by having a switched oscillator driving directly the antenna. The two versions of the transmitters were designed in 65nm CMOS technology from GF. One consumed 3.3mW of power while delivering -2dBm of power to the output, while the other consumed 5mW of power while delivering 2dBm of power to the output. A third topic of this thesis is the design of a novel all-digital phase-locked loop (DPLL) which can be used in the transmitter to synchronize the data and the oscillator clock. The design can be modified and used as a clock and data recovery on the receiver side. The proposed DPLL can be used as a frequency demodulator without any changes to the original architecture. The DPLL was simulated using 65nm CMOS. An operating range of one decade was achieved (20MHz-220MHz) while consuming a power of less than 100uW.
Date of AwardMay 2015
Original languageAmerican English
SupervisorAyman Shabra (Supervisor)


  • Wireless Sensor Networks
  • Transmitter
  • Transceiver
  • Wireless Sensor Nodes On
  • Phase-Locked Loop.

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