Low Power Memory Design

  • Ayman Rizk

Student thesis: Master's Thesis


With the current trend of super handheld computing devices like the iPad, low power memory devices are necessary. Research has commenced to determine how Nanotechnology can be utilized to achieve this goal. This includes the use of nanowires or nanoparticles to enhance the performance of nano-memory devices. This thesis project investigates two promising types of nano-memories as an ultra-low power alternative to today's mainstream memories which are facing now a number of issues with the continuous scaling and portability of today's devices: a volatile memory that combines the best of two worlds; the SRAM speed and DRAM scale and cost, along with a non-volatile memory that is able to help extend Moore's law: (1) The volatile memory studied with TCAD (Technology Computer Aid Design) is a One-transistor (1T) Nanowire memory, which helps to extend the DRAM roadmap by removing the capacitor; besides, significantly reducing the fabrication cost. This novel Si Nanowire 1T DRAM memory utilizes gate work-function and voltage to create barriers or 'doping' like areas to trigger a positive feedback effect which allows achieving a remarkably low-voltage operation with extremely long retention times as it doesn't need to be refreshed as frequent as a conventional DRAM. The device utilizes high-k metal gate technology and can be fabricated using a standard SOI CMOS process. (2) The non-volatile memory fabricated is a ZnO charge trap memory. Charge trap memory is simple in structure, provides better scaling of cell size, has low operating voltage and is able to suppress the charge loss from the stress induced leakage current (SILC) has made it the best candidate to replace the flash memory and overcome its scaling limitations; since the conventional flash memory, a single defect can discharge the whole stored charge of the device due to the conductive properties of the floating poly-silicon gate electrode. However, for the case of the charge trap memory device the charges are stored in discrete traps, so a single defect will not cause the discharge of the whole memory. Furthermore we show with TCAD that the performance of the ZnO memory can be improved dramatically with embedded nanoparticles, which allow for a reduced operating voltage and a larger memory effect.
Date of AwardMay 2012
Original languageAmerican English
SupervisorAmmar Nayfeh (Supervisor)


  • Memory management (Computer science)
  • Technology- Computer-assisted instruction.

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