Integrated Photonic Devices Design and Characterization for Data Communication Networks and AI Accelerators

Abstract

The bandwidth and speed constraints within the microchips of the data centers and computing systems can be mitigated by implementing a high data rate switching system in very compact and small-footprint integrated photonic chips. Photonic devices for high-speed optical data communication are tremendously increasing, aiming at enabling high-speed and energyefficient optical transmissions. Consequently, the investigation and implementation of configurable high-speed and parallel data transmission enablers for photonic devices such as wavelength division multiplexing (WDM), modulators, phase shifters, etc., started a long time ago. WDM is one of the most efficient multi-access techniques in optical communications, enhancing the data interconnections' aggregated channel capacity. In this Ph.D. study, we design and experimentally demonstrate a novel and more robust WDM filter system for highspeed data center optical interconnection based on a silicon and silicon nitride (SiN) platform. In this work, we design, simulate, and experimentally verify a ring-based WDM filter and a grating-based contra-directional couplers (CDCs) course WDM (cWDM). The CDCs cWDM is organized in two different configuration setups: a straight-distributed Bragg reflector (SDBR) and a curved-distributed Bragg reflector (CDBR).

A stable eight-channel SiN-ring resonator-based WDM filter with a channel bandwidth of 50 GHz and 100 GHz channel spacing is designed and implemented in first, second, and thirdorder filter configurations. The designed third-order WDM ring-based filter achieves a 50 GHz bandwidth, 31 dB inter-channel cross talk, optical band rejection ratio (OBRR) of 51 dB, extinction ratio (ER) of 48 dB, and 100 GHz channel spacing. In addition, we design and experimentally demonstrate grating-assisted based CDCs wavelength selective filters for coarse WDM. In this design, the side-lobes strength of the transmission spectrum is suppressed by controlling the energy exchange between the asymmetric waveguides of the CDC using grating and spacing apodization. In doing so, the side lobes suppression ratio of 32 dB and 25 dB in the SDBR and CDBR, respectively, is achieved. The experimental characterization demonstrates a flat-top and low insertion loss (0.43 dB) spectrally stable performance (<0.7 nm spectral shift) across several different wafer test sites. The devices have a compact footprint of only 0.00013 mm2/ch (SDBR) and 0.0024 mm2/ch (CDBR).

Implementing configurable silicon photonics for data communication and/or artificial intelligence (AI) accelerators requires tunable optical devices that can quickly learn and enable fast inferences. It is uncommon to implement high-density reconfigurable integrated photonic circuits without phase shifters for tuning purposes. Accordingly, we investigate different thermo-optics phase shifter configuration setups. A power-efficient thermo-optics phase shifter (TOP) is designed and fabricated for photonic neural networks and data-switching applications. Numerous geometrical variation analyses of heater dimensions are performed for the detailed performance analysis of the thermo-optics phase shifter. The optimisation is conducted for two different TOP configurations, MZM-based TOP and RAMZM-based TOP. Accordingly, both designs are experimentally verified to enable the ‘π’ phase shift with only 21 mW and 2.4 mW for MZM-based and RAMZM-based, respectively. In addition, the thermal crosstalk is observed to be lower than 0.5 K at a maximum lateral distance of 11 µm from the heat source. Furthermore, a new MZM-based TOP configuration with enhanced thermal efficiency of 16 mW is numerically verified to be implemented in photonic neural networks.

Both designed TOPs, MZM-based and RAMZM-based TOPs, are the core components in newly emerging applications such as Photonic Neural Networks (PNNs). In PNN, the optical interference unit (OIU) uses TOPs to adjust the weights and train the neural network. In this work, we designed and simulated power-efficient silicide-based heaters for PNN. In silicide TOP, unlike metal heaters, thermal diffusion is through silicon (Si), and unlike doped heaters, there is no free-carrier absorption. Accordingly, silicide-based TOPs require relatively lower power (Pπ = 16 mW) to induce a change in the effective index, which corresponds to a phase shift. Therefore, they are promising in power-demanding PNN applications. Accordingly, a configurable photonic neural network for digital logic (OR, AND, NAND, and XOR) is implemented by integrating the designed TOPs. We propose and design a compact 3 × 3 PNN using a mesh of MZMs with a phase shifter on one of the arms. Despite using only a singlephase shifter, the device was successfully trained for linearly and non-linearly separable logic operations. Implementation of only one phase shifter yielded a compact network that can perform tasks with an accuracy as high as 99.4% for a linearly separable dataset with a single hidden layer.

Lastly, all-optical devices, including ring-based and DBR-based filters and thermal phase shifters, are designed and fabricated for high-speed data communication networks and optical neural networks. The devices are fabricated on a CMOS-compatible state-of-the-art monolithic silicon photonics platform, enabling on-chip integration of electronics and photonic devices, and can be integrated into high-speed data center optical interconnections and AI accelerators.

Date of Award	Dec 2022
Original language	American English
Supervisor	JAIME Viegas (Supervisor)