End-to-End ECG Processor for Edge Devices

Abstract

The Electrocardiogram (ECG) signal, which can be captured with simple diagnostic tools, has been used in diagnosing a variety of heart arrhythmias. Several machine-learning techniques have been developed to correctly classify ECG signals based on various extracted features. However, the advancement of deep learning techniques eliminated the need for explicitly defining the models and the classification accuracy of ECG signals has improved dramatically as deep neural networks (DNN) can be trained to self-learn useful representative features of arrhythmias from raw ECG waveforms. The superior accuracy of DNNs is achieved at a cost of high computational complexity due to the large number of hidden layers. In the first contribution of this thesis, a shallow neural network with recurrent output was developed, trained and tested using dataset obtained from QT database for detecting the QRS complex (a feature that is crucial for auto-diagnosis of various cardiopathies). The trained model was then implemented using ASIC (Application Specific Integrated Circuit) flow achieving an accuracy of 97.18%. A high-level performance evaluation was also carried out using the same network for P and T wave extraction and achieved comparable accuracy result. The weight and bias matrices obtained from the high-level trained network in MATLAB were used in the design of a hardware implementation of the neural network. An accuracy of 96.55% was achieved in the hardware implementation of the network for the QRS samples detection. The second contribution introduces a novel one-dimensional ShuffleNet based model. The model was developed and trained using a dataset obtained from AHA database for an end-to-end arrhythmia classification task. Moreover, a novel encoding scheme of the window for training and test set samples was employed, allowing the model to detect multiple classes in one sample. Furthermore, to start a baseline hardware implementation for future work, the conventional Convolutional Neural Network (CNN) model was then mapped into a hardware architecture and coded designed in Verilog Register Transfer Level (RTL) hardware description language. FSM (finite state machine) was developed to control the dataflow in the closed loop architecture where the hardware resources and the memory size is reused for activation features of all layers. Synthesis report of the hardware implementation shows that the accelerator consumes a power of 9.13 mW and occupies a design area of 2.1mm2. With 20x times less number of trainable parameters, our model has outperformed traditional CNN achieving an F1-score of 95%.

Date of Award	May 2020
Original language	American English