Efficient Power Management for Low Power Wearable Electronics

Abstract

With the dramatic rise of mobile electronic devices usage especially as an effect of the internet of things revolution, the demand for energy efficient and small form factor systems raises the need for low power multisource management unit (PMU) for energy strained devices as well as energy harvesting as alternative power source in many usage scenarios. In this thesis, an efficient PMU targeting low power wearable electronic devices is developed. The first part of the thesis presents a thermoelectric generator (TEG) energy harvesting-based PMU where several design options of DC-DC converters have been evaluated and characterized using 65nm LPE CMOS. This part is considered as a guide for the designers to select the suitable PMU according to the block requirements. Due to the TEG voltage level constraints, a high boost ratio inductor-based converter with a maximum power point transfer is utilized for a power conversion purpose followed by an analog LDO and/or a switched capacitor for voltage regulation purpose. The cascaded PMU of inductor-based converter followed by an analog LDO is recommended for RF blocks due to its low voltage ripple whereas the cascaded PMU of the inductor- based converter followed by a switched capacitor is recommended for digital blocks because they tolerates relatively high ripple and require high voltage conversion ratio. The maximum end-to-end achieved efficiency of the cascaded PMU design is 65%. The second part of the thesis presents an area and power efficient dual-outputs switched capacitor (DOSC) DC-DC buck converter. This part of the thesis high lights how the digital circuit can be used to configure the switched capacitor to generate simultaneous two output voltages while minimizing the active area. An 800nW fully digital adaptive time multiplexing (ATM) control technique is employed to generate two output voltages using a single SC to reduce the area. The ATM is further improved to completely eliminate the reverse current and reduce the output voltage droop by 40mV. The DOSC is fabricated in 65nm CMOS technology. The third part of the thesis presents a novel ratioed logic comparator-based digital LDO (RLC-DLDO) that solves the speed-power tradeoff by removing the digital loop delay introduced by the clocked comparator and synchronous SR in the conventional design. The proposed RLC-DLDO implements a low power asynchronous ratioed logic comparator that reacts continuously to the load transient to ensure a faster response.The RLC-DLDO achieves a transient speed improvement in the ns range and a current reduction including quiescent and switching by 9X over the conventional design with 1MHz clock frequency. The RLC-DLDO is fabricated in 22nm FDSOI technology.

Date of Award	Jun 2019
Original language	American English