Design And Optimization Of Charge Pump For Energy Harvesting System

Abstract

The goal of this thesis is to explore, design and develop an efficient hardware implementation of a charge pump to be used for energy harvesting based system. A power management unit that includes charge pump and the control circuitry to perform the regulation is developed. Traditional Charge pump has limited discrete voltage levels determined by the number of stages. In contrast, the proposed system provides more flexibility in generating more granular voltage levels to achieve high energy efficiency. Both frequency and stage modulation have been utilized in the proposed design. The stage modulation provides a coarse voltage level while the frequency modulation provides more granular level. In addition, the usage of smaller number of stages to generate a certain voltage level can be achieved by circulating the output voltage to the previous stage. A decoder is used to select the number of stages that are needed using two control bits to perform the stage modulation. Using four-stages charge pump, Spice simulation in 65 nm CMOS technology showed a maximum efficiency of 76% at input voltage of 0.5 V. The system supports a range of load current between 1 nA – 24 μA with a maximum operating frequency of 2MHz. The proposed system supports an input voltage range from 0.4 to 0.6 V which can be used in energy harvesting applications. Furthermore, a novel, energy efficient and high boosting ratio two-dimensional charge pump (2DCP) is developed. The proposed 2DCP has the same operating principle as the conventional Dickson charge pump (DCP). However, it has higher output voltage for the same number of stages compared to the state-of-art charge pumps. 2DCP is designed by combining multiple DCP in parallel and series configurable combination. Hence, 2DCP can boost the input voltage at much higher rate compared to the DCP. A mathematical analysis and derivation of the output voltage for 2DCP is provided, which clearly shows the advantage of the proposed circuit. The 2DCP provides 1.44 higher boosting ratio than the DCP when 14 stages are implemented. SPICE simulation in 65 nm CMOS process confirms the performance and pumping efficiency of the 2DCP.

Date of Award	Jun 2017
Original language	American English
Supervisor	Baker Mohammad (Supervisor)