CMOS Transceiver Circuits for Nano-Photonic Links in Data Centers

  • Solomon Micheal Serunjogi

Student thesis: Doctoral Thesis


Recently, the demand for high bandwidth (BW) and low latency applications such as cloud computing video streaming and scientific research, has resulted in the proliferation of large-scale data-centers (DCs) around the world. These centers consist of data-aggregation servers at the application layer of the open source interconnect (OSI) model interconnected by, previously long-haul optical fiber links, and recently, short optical communication links. Current technology capabilities allow these centers to transmit a maximum of 100Gb/s by multiplexing 4 optical fiber channels of 25Gb/s. However, as demand for bandwidth exponentially increases, data-centers are proposing capacity upgrades to 400Gb/s and beyond. These upgrades, come with serious technical challenges: e.g. we would need 8x25 Gb/s vertical surface emitting laser (VCSELs) sources at the transmitter and 8x25Gb/s photodiodes (PDs) at the receiver, in order to achieve 400 Gb/s. Scaling this even further, to 1Tb/s, would require 40 VCSELs and 40 PDs in the same setup. This puts a heavy price on key figures-of-merit such power consumption, integration density and scalability. Furthermore, the burst nature of the DC traffic requires peripheral clock and data recovery digital circuits that operate at the transport layers of the OSI model, to comply with such switching speeds. Therefore, future communication links need novel architectures that fundamentally improve bandwidth for a single channel beyond the current 25Gb/s per channel. In line with the above discussion, this thesis addresses the problem as follows: 1) Review of complex modulation formats that are best suited for future datacenters (both amplitude and phase modulated links). 2) Linearity analysis of microwave photonic links using Volterra series. Here, a new optical discriminator filter for phase modulated links are also presented: these are based on finite impulse response (FIR) and autoregressive moving average (ARMA) digital filter techniques. 3) Design and analysis of non-return-to-zero (NRZ) burst-mode transceiver front ends (Receiver and Transmitter) operating at 64Gb/s using positive and negative feedback compensation. In particular, attention was paid to broadband drivers with large swing capabilities. The transceivers are realized in 65nm CMOS technology from Global Foundries. 4) The theoretical design tradeoffs of clock and data recovery (CDRs) circuits and phase locked loops (PLLs) are studied. These include cycle-to-cycle-jitter in time domain and closed loop stability of 2nd and 3rd order PLLs in frequency domain.
Date of AwardMay 2017
Original languageAmerican English
SupervisorMahmoud Rasras (Supervisor)


  • Data Centers
  • Data Transfer Rates
  • High Bandwidth
  • Optical Transfer
  • Laser Transmitters

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