CMOS High Efficiency and Linearity Transmitters for Wireless Communications

Abstract

The ability to support multiple communication standards by mobile devices has become a necessity with the unceasing evolution of wireless technologies. Furthermore, the growing wish of saving fabrication cost and achieving smaller form factor has made high level of integration become more and more important. At present, multiple radios operate at predefined sets of modulation schemes, frequency bands, bandwidths, and output power levels in order to accommodate the existing wireless technologies such as 3G/LTE, WLAN, or Bluetooth. This results in high component counts and increased cost. In order to tackle these issues and make the radio solution reconfigurable, the Radio Frequency Integrated Circuit (RFIC) along with its main constituent, the power amplifier (PA) has to become more flexible by supporting different existing technologies, coping with different future user-case scenarios, while most importantly preserving the handset's battery life. Moreover, achieving a single-chip radio solution is also vital, especially with the bottleneck formed by the PA as a result of its poor compatibility with modern Complementary Metal Oxide Semiconductor (CMOS) technology as well as its low average power efficiency.This research addresses these issues by presenting a highly efficient and linear CMOS transmitter for wireless communications. A novel modulation scheme capable of driving highly efficient switched-mode power amplifiers (SMPA) was used. In addition, the design, analysis and implementation of a CMOS PA that is amenable to the proposed scheme will be discussed. A modified current mode class-D, more generally known as inverse class-D (or class-D -1 ) PA architecture has been proposed and realized in 65 nm CMOS technology. The designed PA yielded a record peak drain efficiency of 78.5% while delivering an output power of ~1W at 1 GHz frequency. For the best of our knowledge, this is the first CMOS PA delivering 1.52 W (31.82 dBm) to the load antenna with the given efficiency. Moreover, to lend satisfactory amplitude to the incoming modulated signals to drive the output stage, design of a high speed buffer (driver) in CMOS has also been undertaken. Finally, an output matching network along with a bandpass filter has been designed to ensure linearity is achieved while satisfying the spectral emission mask for WLAN 802.11a and 4G LTE standards.

Date of Award	May 2017
Original language	American English
Supervisor	Mihai Sanduleanu (Supervisor)