An ECG signal processor for the Prediction of ventricular arrhythmia

Abstract

During the last decades, medical wearable devices have gain lots of interest due to their potential influence in providing remote and ambulatory monitoring to support patients. Many devices have been developed, improved, and implemented for the long-term and continuous monitoring of the healthcare practices in general and cardiovascular diseases in particular. Due to its eficiency, simplicity and noninvasiveness, the Electrocardiogram (ECG) signal has been widely used for monitoring cardiac functions despite the development of newer techniques or technologies. The information contained in the morphological features of the ECG signal has been broadly employed to build a full classification system capable of distinguishing between normal and abnormal conditions. This thesis presents the first ASIC implementation of an ECG-based signal processor (ESP) that is capable of predicting ventricular arrhythmia up to 3-hours before the onset. The ESP is composed of three stages which include ECG signal processing, feature extraction and classification, and it utilizes adaptive and novel techniques that are highly effective and suitable for real-time implementation. The extracted ECG features, individually and in combinations, showed good potential in the prediction of ventricular arrhythmia with significant statistical results and the combination of the these features has never been used in any previous detection or prediction system. Two databases of heart signal recordings from MIT Physionet and the American Heart Association (AHA) were used as training, test, and validation sets to evaluate the performance of the proposed system. Based on Matlab testing results, the proposed system achieved a prediction accuracy (ACC) of 99.98% on the out-of-sample validation data by tenfold cross validation with 3{sec window size. Furthermore, the proposed ESP was developed using Verilog RTL and implemented using ASIC implementation low based on 65 nm global foundries low power CMOS process. Based on the design constraints, the ESP occupied a state-of-the-art total cell area of 0.112 mm2 and consumed a total power of 2.78 W at an operating frequency of 10 kHz and operating voltage of 1.2 V.

Date of Award	2015
Original language	American English
Supervisor	Hani Saleh (Supervisor)