An 8-bit sub-range Time-Domain ADC

Abstract

Throughout the years, the process of electronic technology scaling have continued which ensued in faster, cheaper and lower power devices. However, the reduction of the device geometry results in the increase of the device's parameter variation and the reduction in supply voltage caused the dynamic range as well as the signal-to-noise-ratio to diminish. Consequently, designing voltage-domain analog-to-digital converter (ADC) becomes problematic especially when targeting high speed and large resolution applications. Nonetheless, technology scaling results in the reduction in the gate delays making processing in time domain less challenging. Thus, it is beneficial to use time domain as an intermediate conversion step in order to exploit the advantages it has to offer. This thesis presents an 8-bit time domain based ADC which consists of a linear voltage-to-time converter (VTC) and a coarse-fine time-to-digital converter (TDC). The proposed work was implemented in 65nm low power foundry technology. One of the crucial tasks throughout the design process, is obtaining a linear VTC that is composed of a track and hold circuit and voltage control delay lines (VCDL). The track and hold circuit underwent a two tone intermodulation distortion test and achieved a third order intercept point (IIP3) of 39.7dBm while the VCDL output deviated from the regression line by 8.6273zs. Furthermore, the ADC resolution is dictated by the smallest time interval that the TDC can digitize that is the di↵erential delay between the vernier delay line cells which is approximately 78ps.

Date of Award	Mar 2020
Original language	American English