A time-interleaved adc for high data rate wireless receivers

  • Yue. Xu

Student thesis: Master's Thesis

Abstract

The demand for higher data rate in wireless communication has driven researchers to explore higher frequency bands, such as millimeter-wave band. Although advancements in the CMOS technologies make it feasible to design circuits for such high frequencies, circuit designers are facing new sets of challenges, especially at the front end. High data-rate low-power analog-to-digital converter (ADC) is one of the design challenges. The focus of this work is designing an analog-to-digital converter for a very high data-rate wireless receiver. It includes two major parts: 1) A time-interleaving ADC architecture that exploits correlations between samples. This architecture relies on the extra information that results from oversampling the input to predict the range of the next sample, using predictive algorithms. Comparators that are outside the predicted range can be turned off; and power can be saved. We compared the behavioral simulation results of two predictive algorithms (last sample prediction and linear extrapolation prediction). Results show that the predictive algorithms promise to reduce power consumption. 2) A novel hybrid flash-time-to-digital (TDC) ADC. This architecture utilizes the comparator's output timing information to resolve the lower bits. The design challenges include the metastability issue of D flip-flops, sampling at a high frequency while maintaining low power, sensitivity to layout, large process variation, inaccuracy of post-layout extraction seen in 28nm process node. Details of building blocks (comparator, TDC, mapping logic, and clock generator) are presented. Schematics-level simulation results are presented.
Date of Award2013
Original languageAmerican English
SupervisorAyman Shabra (Supervisor)

Keywords

  • Major Electrical Engineering. | Microsystems Engineering | low pwer consumption circuit.

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