A Low Power Clocking Architecture with Sub-Picosecond Resolution Tunable Delays for a mm-Wave Beam Forming Receiver

Abstract

The exploding demand for high speed wireless data has driven researchers to explore the millimeter-wave frequency band and its enabling technologies including antenna beam forming. A novel antenna beam forming receiver that relies on adjusting the delay of the sampling clock was shown to overcome many of the performance limitations of the conventional designs. The proper functionality of the proposed beam forming approach critically depends on the design of digitally tunable delay units with sub-picosecond delay resolution and jitter and low power. Digitally adjustable delay or phase circuits are also essential for many other applications including clock and data timing recovery, frequency synthesis and time-mode signal processing. The simplest variable delay circuits generate uniformly incremental delay values by utilizing a simple chain of cascaded delay buffers in open loop or a delay-locked loop (DLL). Such circuits are fundamentally limited in resolution by the minimum delay of a single buffer. Direct phase interpolation overcomes this limitation while incurring a significant design complexity. As an alternative, open-loop delay lines with fine digital control have been proposed in literature. Such open-loop designs suffer from high sensitivity to PVT variations. This thesis introduces a simple and novel DLL based architecture that eliminates the complexities of direct phase interpolation. The fine tuning of delay is achieved by controlling the number of in-loop delay line buffers using a multiplexer and a feedback error interpolator which can emulate a fractional number of loop buffers. The adopted architecture has the advantages of simplicity, high resolution and robustness. System-level analysis of the adopted architecture using MATLAB shows its adaptability to different design requirements and ability to generate a very small delay step with a low interpolator resolution. A novel proposed transistor-level realization of the architecture is simulated in 65 nm CMOS technology where the interpolation is performed by weighting the current of two charge pumps. In schematic-level simulation, we have demonstrated a delay resolution of 0.3 ps and a worst-case RMS jitter less than 0.2 ps over a delay span of 25.5 ps, and a power consumption roughly less than 1.5 mW with a 2 GHz input clock.

Date of Award	2014
Original language	American English
Supervisor	Ayman Shabra (Supervisor)