VLSI implementation of 16-point DCT for H.265/HEVC using walsh hadamard transform and lifting scheme

Ashfaq Ahmed; Muhammad Awais; Martina Maurizio; Guido Masera

doi:10.1109/INMIC.2011.6151460

VLSI implementation of 16-point DCT for H.265/HEVC using walsh hadamard transform and lifting scheme

Ashfaq Ahmed, Muhammad Awais, Martina Maurizio, Guido Masera

Electrical Engineering

Politecnico di Torino

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

12 Scopus citations

Abstract

In this paper, a fast 16-point DCT is implemented using a multiplier-less architecture. The 16-point DCT matrix is decomposed into sparse sub-matrices in order to reduce the multiplications and finally the multiplications are completely eliminated using the lifting scheme. Therefore, the computational complexity of the architecture is much lower than the direct implementation of 16-point DCT. In software implementation, 45 dB of PSNR is achieved for the "Lena" image. The VLSI implementation has been carried out for a 90-nm standard cell technology at a clock frequency of 150 MHz.

Original language	British English
Title of host publication	Proceedings of the 14th IEEE International Multitopic Conference 2011, INMIC 2011
Pages	144-148
Number of pages	5
DOIs	https://doi.org/10.1109/INMIC.2011.6151460
State	Published - 2011
Event	14th IEEE International Multitopic Conference 2011, INMIC 2011 - Karachi, Pakistan Duration: 22 Dec 2011 → 24 Dec 2011

Publication series

Name	Proceedings of the 14th IEEE International Multitopic Conference 2011, INMIC 2011

Conference

Conference	14th IEEE International Multitopic Conference 2011, INMIC 2011
Country/Territory	Pakistan
City	Karachi
Period	22/12/11 → 24/12/11

Keywords

Discrete Time Cosine Transform (DCT)
High Efficiency Video Coding (HEVC)
PSNR (Peak Signal to Noise Ratio)
WHT (Walsh Hadamard Transform)

Access to Document

10.1109/INMIC.2011.6151460

Cite this

Ahmed, A., Awais, M., Maurizio, M., & Masera, G. (2011). VLSI implementation of 16-point DCT for H.265/HEVC using walsh hadamard transform and lifting scheme. In Proceedings of the 14th IEEE International Multitopic Conference 2011, INMIC 2011 (pp. 144-148). Article 6151460 (Proceedings of the 14th IEEE International Multitopic Conference 2011, INMIC 2011). https://doi.org/10.1109/INMIC.2011.6151460

@inproceedings{429f6cdfebb7411482ab498c27f82e3a,

title = "VLSI implementation of 16-point DCT for H.265/HEVC using walsh hadamard transform and lifting scheme",

abstract = "In this paper, a fast 16-point DCT is implemented using a multiplier-less architecture. The 16-point DCT matrix is decomposed into sparse sub-matrices in order to reduce the multiplications and finally the multiplications are completely eliminated using the lifting scheme. Therefore, the computational complexity of the architecture is much lower than the direct implementation of 16-point DCT. In software implementation, 45 dB of PSNR is achieved for the {"}Lena{"} image. The VLSI implementation has been carried out for a 90-nm standard cell technology at a clock frequency of 150 MHz.",

keywords = "Discrete Time Cosine Transform (DCT), High Efficiency Video Coding (HEVC), PSNR (Peak Signal to Noise Ratio), WHT (Walsh Hadamard Transform)",

author = "Ashfaq Ahmed and Muhammad Awais and Martina Maurizio and Guido Masera",

year = "2011",

doi = "10.1109/INMIC.2011.6151460",

language = "British English",

isbn = "9781457706554",

series = "Proceedings of the 14th IEEE International Multitopic Conference 2011, INMIC 2011",

pages = "144--148",

booktitle = "Proceedings of the 14th IEEE International Multitopic Conference 2011, INMIC 2011",

note = "14th IEEE International Multitopic Conference 2011, INMIC 2011 ; Conference date: 22-12-2011 Through 24-12-2011",

}

Ahmed, A, Awais, M, Maurizio, M & Masera, G 2011, VLSI implementation of 16-point DCT for H.265/HEVC using walsh hadamard transform and lifting scheme. in Proceedings of the 14th IEEE International Multitopic Conference 2011, INMIC 2011., 6151460, Proceedings of the 14th IEEE International Multitopic Conference 2011, INMIC 2011, pp. 144-148, 14th IEEE International Multitopic Conference 2011, INMIC 2011, Karachi, Pakistan, 22/12/11. https://doi.org/10.1109/INMIC.2011.6151460

VLSI implementation of 16-point DCT for H.265/HEVC using walsh hadamard transform and lifting scheme. / Ahmed, Ashfaq; Awais, Muhammad; Maurizio, Martina et al.
Proceedings of the 14th IEEE International Multitopic Conference 2011, INMIC 2011. 2011. p. 144-148 6151460 (Proceedings of the 14th IEEE International Multitopic Conference 2011, INMIC 2011).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - VLSI implementation of 16-point DCT for H.265/HEVC using walsh hadamard transform and lifting scheme

AU - Ahmed, Ashfaq

AU - Awais, Muhammad

AU - Maurizio, Martina

AU - Masera, Guido

PY - 2011

Y1 - 2011

N2 - In this paper, a fast 16-point DCT is implemented using a multiplier-less architecture. The 16-point DCT matrix is decomposed into sparse sub-matrices in order to reduce the multiplications and finally the multiplications are completely eliminated using the lifting scheme. Therefore, the computational complexity of the architecture is much lower than the direct implementation of 16-point DCT. In software implementation, 45 dB of PSNR is achieved for the "Lena" image. The VLSI implementation has been carried out for a 90-nm standard cell technology at a clock frequency of 150 MHz.

AB - In this paper, a fast 16-point DCT is implemented using a multiplier-less architecture. The 16-point DCT matrix is decomposed into sparse sub-matrices in order to reduce the multiplications and finally the multiplications are completely eliminated using the lifting scheme. Therefore, the computational complexity of the architecture is much lower than the direct implementation of 16-point DCT. In software implementation, 45 dB of PSNR is achieved for the "Lena" image. The VLSI implementation has been carried out for a 90-nm standard cell technology at a clock frequency of 150 MHz.

KW - Discrete Time Cosine Transform (DCT)

KW - High Efficiency Video Coding (HEVC)

KW - PSNR (Peak Signal to Noise Ratio)

KW - WHT (Walsh Hadamard Transform)

UR - http://www.scopus.com/inward/record.url?scp=84858027101&partnerID=8YFLogxK

U2 - 10.1109/INMIC.2011.6151460

DO - 10.1109/INMIC.2011.6151460

M3 - Conference contribution

AN - SCOPUS:84858027101

SN - 9781457706554

T3 - Proceedings of the 14th IEEE International Multitopic Conference 2011, INMIC 2011

SP - 144

EP - 148

BT - Proceedings of the 14th IEEE International Multitopic Conference 2011, INMIC 2011

T2 - 14th IEEE International Multitopic Conference 2011, INMIC 2011

Y2 - 22 December 2011 through 24 December 2011

ER -

Ahmed A, Awais M, Maurizio M, Masera G. VLSI implementation of 16-point DCT for H.265/HEVC using walsh hadamard transform and lifting scheme. In Proceedings of the 14th IEEE International Multitopic Conference 2011, INMIC 2011. 2011. p. 144-148. 6151460. (Proceedings of the 14th IEEE International Multitopic Conference 2011, INMIC 2011). doi: 10.1109/INMIC.2011.6151460

VLSI implementation of 16-point DCT for H.265/HEVC using walsh hadamard transform and lifting scheme

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