@inproceedings{a59ae4be301141b1ab6c4864028bc7ec,
title = "VLSI architectures for blind equalization based on fractional-order statistics",
abstract = "Four types of VLSI architectures for the hardware realization of the FLOS-CM algorithm are introduced in this paper. Each architecture is appropriate for a particular environment. The FLOS-CM algorithm is found to be amenable for implementation using logarithmic arithmetic. A logarithmic architecture is shown to require up to 50% less area and be 14% faster than a linear fixed-point arithmetic counterpart. In terms of Area×Time and Area×Time 2 complexities, the logarithmic architecture is up to 120% better.",
author = "V. Paliouras and J. Dagres and P. Tsakalides and T. Stouraitis",
year = "2001",
language = "British English",
isbn = "0780370570",
series = "Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems",
pages = "799--802",
booktitle = "ICECS 2001 - 8th IEEE International Conference on Electronics, Circuits and Systems",
note = "8th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2001 ; Conference date: 02-09-2001 Through 05-09-2001",
}