Very-Long Instruction Word Digital Signal Processor based on the Logarithmic Number System

The organization and the VLSI implementation of a Very Long Instruction Word (VLIW) Digital Signal Processor are discussed in this paper. The processor operates in the Logarithmic Number System (LNS) and it features two LNS execution units. Each execution unit contains a single-clock multiply/divide unit and a pipelined adder/subtractor of dynamic range equivalent to the single-precision IEEE 754 standard requirements. The architecture is optimized for the execution of FIR and IIR filters, as well as any sum-of-products based digital signal processing algorithm. The full exploitation of the independent resources is facilitated by porting the complexity of resolving the dependencies among the instructions from special control hardware to the organization of the application software, an off-line task. The main characteristics of the introduced processor include the ability to issue concurrently up to thirty elementary instructions, the two LNS execution units including division, and the dynamic range offered by the 33-bit data word. The chip has been designed and simulated in a commercial 0.7-μm CMOS technology.