Tin (Sn) for enhancing performance in silicon CMOS

Aftab M. Hussain; Hossain M. Fahad; Nirpendra Singh; Galo A. Torres Sevilla; Udo Schwingenschlögl; Muhammad M. Hussain

doi:10.1109/NMDC.2013.6707470

Tin (Sn) for enhancing performance in silicon CMOS

Aftab M. Hussain, Hossain M. Fahad, Nirpendra Singh, Galo A. Torres Sevilla, Udo Schwingenschlögl, Muhammad M. Hussain

Physics

King Abdullah University of Science and Technology

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

2 Scopus citations

Abstract

We study a group IV element: tin (Sn) by integrating it into silicon lattice, to enhance the performance of silicon CMOS. We have evaluated the electrical properties of the SiSn lattice by performing simulations using First-principle studies, followed by experimental device fabrication and characterization. We fabricated high-κ/metal gate based Metal-Oxide-Semiconductor capacitors (MOSCAPs) using SiSn as channel material to study the impact of Sn integration into silicon.

Original language	British English
Title of host publication	IEEE Nanotechnology Materials and Devices Conference, IEEE NMDC 2013
Publisher	IEEE Computer Society
Pages	13-15
Number of pages	3
ISBN (Print)	9781479933877
DOIs	https://doi.org/10.1109/NMDC.2013.6707470
State	Published - 2013
Event	2013 IEEE 8th Nanotechnology Materials and Devices Conference, IEEE NMDC 2013 - Tainan, Taiwan, Province of China Duration: 6 Oct 2013 → 9 Oct 2013

Publication series

Name	IEEE Nanotechnology Materials and Devices Conference, IEEE NMDC 2013

Conference

Conference	2013 IEEE 8th Nanotechnology Materials and Devices Conference, IEEE NMDC 2013
Country/Territory	Taiwan, Province of China
City	Tainan
Period	6/10/13 → 9/10/13

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10.1109/NMDC.2013.6707470

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Hussain, A. M., Fahad, H. M., Singh, N., Torres Sevilla, G. A., Schwingenschlögl, U., & Hussain, M. M. (2013). Tin (Sn) for enhancing performance in silicon CMOS. In IEEE Nanotechnology Materials and Devices Conference, IEEE NMDC 2013 (pp. 13-15). Article 6707470 (IEEE Nanotechnology Materials and Devices Conference, IEEE NMDC 2013). IEEE Computer Society. https://doi.org/10.1109/NMDC.2013.6707470

@inproceedings{45ca206fcf404de9bdbceb60e0218fb7,

title = "Tin (Sn) for enhancing performance in silicon CMOS",

abstract = "We study a group IV element: tin (Sn) by integrating it into silicon lattice, to enhance the performance of silicon CMOS. We have evaluated the electrical properties of the SiSn lattice by performing simulations using First-principle studies, followed by experimental device fabrication and characterization. We fabricated high-κ/metal gate based Metal-Oxide-Semiconductor capacitors (MOSCAPs) using SiSn as channel material to study the impact of Sn integration into silicon.",

author = "Hussain, {Aftab M.} and Fahad, {Hossain M.} and Nirpendra Singh and {Torres Sevilla}, {Galo A.} and Udo Schwingenschl{\"o}gl and Hussain, {Muhammad M.}",

year = "2013",

doi = "10.1109/NMDC.2013.6707470",

language = "British English",

isbn = "9781479933877",

series = "IEEE Nanotechnology Materials and Devices Conference, IEEE NMDC 2013",

publisher = "IEEE Computer Society",

pages = "13--15",

booktitle = "IEEE Nanotechnology Materials and Devices Conference, IEEE NMDC 2013",

address = "United States",

note = "2013 IEEE 8th Nanotechnology Materials and Devices Conference, IEEE NMDC 2013 ; Conference date: 06-10-2013 Through 09-10-2013",

}

Hussain, AM, Fahad, HM, Singh, N, Torres Sevilla, GA, Schwingenschlögl, U & Hussain, MM 2013, Tin (Sn) for enhancing performance in silicon CMOS. in IEEE Nanotechnology Materials and Devices Conference, IEEE NMDC 2013., 6707470, IEEE Nanotechnology Materials and Devices Conference, IEEE NMDC 2013, IEEE Computer Society, pp. 13-15, 2013 IEEE 8th Nanotechnology Materials and Devices Conference, IEEE NMDC 2013, Tainan, Taiwan, Province of China, 6/10/13. https://doi.org/10.1109/NMDC.2013.6707470

Tin (Sn) for enhancing performance in silicon CMOS. / Hussain, Aftab M.; Fahad, Hossain M.; Singh, Nirpendra et al.
IEEE Nanotechnology Materials and Devices Conference, IEEE NMDC 2013. IEEE Computer Society, 2013. p. 13-15 6707470 (IEEE Nanotechnology Materials and Devices Conference, IEEE NMDC 2013).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AU - Hussain, Aftab M.

AU - Fahad, Hossain M.

AU - Singh, Nirpendra

AU - Torres Sevilla, Galo A.

AU - Schwingenschlögl, Udo

AU - Hussain, Muhammad M.

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AB - We study a group IV element: tin (Sn) by integrating it into silicon lattice, to enhance the performance of silicon CMOS. We have evaluated the electrical properties of the SiSn lattice by performing simulations using First-principle studies, followed by experimental device fabrication and characterization. We fabricated high-κ/metal gate based Metal-Oxide-Semiconductor capacitors (MOSCAPs) using SiSn as channel material to study the impact of Sn integration into silicon.

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DO - 10.1109/NMDC.2013.6707470

M3 - Conference contribution

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SN - 9781479933877

T3 - IEEE Nanotechnology Materials and Devices Conference, IEEE NMDC 2013

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BT - IEEE Nanotechnology Materials and Devices Conference, IEEE NMDC 2013

PB - IEEE Computer Society

T2 - 2013 IEEE 8th Nanotechnology Materials and Devices Conference, IEEE NMDC 2013

Y2 - 6 October 2013 through 9 October 2013

ER -

Tin (Sn) for enhancing performance in silicon CMOS

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