TY - GEN
T1 - Timing and robustness analysis of Pulsed-Index protocols for single-channel IoT communications
AU - Muzaffar, Shahzad
AU - Elfadel, Ibrahim M.
N1 - Funding Information:
This work has been supported by the Semiconductor Research Corporation (SRC) under the ATIC-SRC Center of Excellence on Energy-Efficient Electronic Systems (ACE4S), with funding from the Mubadala Development Company, Abu Dhabi, UAE.
Publisher Copyright:
© 2015 IEEE.
PY - 2015/10/30
Y1 - 2015/10/30
N2 - Pulsed-Index Communication (PIC) is a novel technique for single-channel, high-data-rate, low-power dynamic signaling that does not require any clock and data recovery. It is fully adapted to the simple yet robust communication needs of IoT devices and sensors. In this paper, we present a full quantitative analysis of the timing and robustness properties of PIC protocols, including the impact of important protocol parameters such as pulse width and inter-symbol delays on average data rate and protocol robustness with respect to clock variations. The main result of this paper is a theoretical upper bound on clock variability between transmitter and receiver below which the protocol operates with zero decoding error over an ideal channel. This bound is verified experimentally using a full FPGA implementation that includes point-to-point transmission between two TI MSP430 microcontrollers, acting as two IoT sensor nodes over a single-wire connection.
AB - Pulsed-Index Communication (PIC) is a novel technique for single-channel, high-data-rate, low-power dynamic signaling that does not require any clock and data recovery. It is fully adapted to the simple yet robust communication needs of IoT devices and sensors. In this paper, we present a full quantitative analysis of the timing and robustness properties of PIC protocols, including the impact of important protocol parameters such as pulse width and inter-symbol delays on average data rate and protocol robustness with respect to clock variations. The main result of this paper is a theoretical upper bound on clock variability between transmitter and receiver below which the protocol operates with zero decoding error over an ideal channel. This bound is verified experimentally using a full FPGA implementation that includes point-to-point transmission between two TI MSP430 microcontrollers, acting as two IoT sensor nodes over a single-wire connection.
UR - https://www.scopus.com/pages/publications/84960126672
U2 - 10.1109/VLSI-SoC.2015.7314420
DO - 10.1109/VLSI-SoC.2015.7314420
M3 - Conference contribution
AN - SCOPUS:84960126672
T3 - IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC
SP - 225
EP - 230
BT - 2015 IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2015
PB - IEEE Computer Society
T2 - 23rd IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2015
Y2 - 5 October 2015 through 7 October 2015
ER -