Time delay digital tanlock loop with linearized phase detector

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Abstract

This paper presents a time delay digital tanlock loop with a linearized phase detector (TDTL-LPD) architecture. This is achieved through replacement oy the time delay unit oy the TDTL by a variable delay whose phase error is controlled by a feedback mechanism driven by the output oy the inverse tan phase detector. The change in this output is proportional to the changes i. The input signal frequency oy the system. This results in keepin. The quadrature relationship betwee. The two channels that make u. The TDTL. This linearization oy the phase error detector results i. The improvement oy the system performance when used in communication system applications such as FSK (frequency shift keying) demodulation.

Original languageBritish English
Title of host publication2009 16th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2009
Pages555-558
Number of pages4
DOIs
StatePublished - 2009
Event2009 16th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2009 - Yasmine Hammamet, Tunisia
Duration: 13 Dec 200916 Dec 2009

Publication series

Name2009 16th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2009

Conference

Conference2009 16th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2009
Country/TerritoryTunisia
CityYasmine Hammamet
Period13/12/0916/12/09

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