Thermal-driven 3D floorplanning using localized TSV placement

While 3D-ICs help to improve circuit performance and energy efficiency through the reduction of average wirelength and the increase in communication bandwidth of on-chip wiring, their thermal management remains one of the most challenging obstacles to their productization. Placement of thermal through-silicon-vias (TSVs) has been proposed to improve the vertical heat flow in the chip stack and this alleviate the negative impact of heat dissipation on chip performance and reliability. In this paper, we present a novel physical design flow that integrates thermal-driven 3D floorplanning with a novel algorithm for thermal TSVs placement that we call localized TSV placement. The essence of the algorithm is to analyze the layered thermal map of the chip stack and then insert thermal TSVs iteratively until the maximal on-chip temperature is below a pre-selected target. The algorithm is implemented within a full flow for thermal-driven 3D floorplanning. The implementation is tested using several standard benchmarks for physical design, and the experimental results show the suitability of our algorithm for significantly reducing maximum chip temperature at reasonable density levels for thermal TSVs (100° Kelvin reduction at 0.5% TSV density). The larger the die size, the more beneficial the localized placement of thermal TSV's.