@inproceedings{71f6dbcc93694c1abc762314a424cf5f,
title = "The optimum Booth radix for low power integer multipliers",
abstract = "This paper investigates the optimum Booth integer multiplier for low power applications. Booth radix-4, radix-8 and radix-16 were compared for area, speed and power using standard-cell ASIC design flow and 28nm CMOS technology. All of the investigated designs were implemented in RTL, fully verified and then synthesized using 28nm standard-cell libraries which have low leakage slow cells, regular leakage average-speed cells and high-leakage fast-speed cells. The area, speed and power were compared to determine the best choice for low power designs. Among the three investigated designs, the Booth radix-4 was the best choice, it had the lowest area, power and fastest execution speed among the 3-choices. It is worthy of note that radix-8 had lower leakage power and overall power among the three designs when implemented using LVT cells. So for power sensitive and high-speed applications radix-8 could be a better choice with overhead of about 18% area and 3% slower.",
keywords = "28nm CMOS, ASIC, Booth multiplier, radix-16, radix-4, radix-8, standard-cell",
author = "Saleh, {Hani H.} and Mohammad, {Baker S.} and Swartzlander, {Earl E.}",
year = "2013",
doi = "10.1109/IDT.2013.6727119",
language = "British English",
isbn = "9781479935253",
series = "2013 8th IEEE Design and Test Symposium, IDT 2013",
booktitle = "2013 8th IEEE Design and Test Symposium, IDT 2013",
note = "2013 8th IEEE Design and Test Symposium, IDT 2013 ; Conference date: 16-12-2013 Through 18-12-2013",
}