@inproceedings{6b3e5ba3384746e689598b05c6c4cc53,
title = "Technique for frequency transfer over packet networks",
abstract = "This paper describes the design and performance analysis of a new approach for frequency synchronization over packet networks. The technique which includes a digital phase-locked loop (DPLL) is timestamp-based and involves a transmitter clock sending periodically an explicit time indication or timestamp to the receiver so that it can synchronize its local clock to that of the transmitter. The digital oscillator used in the PLL is a divide-by-N counter type oscillator (DNCO). We explain how the DPLL can be designed using standard control theory concepts and show how the DPLL performs in the presence of network perturbations like packet delay variations (PDV) which is the main source of clock errors in packet-based synchronization.",
keywords = "Clock Synchronization, Digital Controlled Oscillator, Divide-by-N counter type oscillator, IEEE 1588, Packet delay variation, Phase-locked loop",
author = "James Aweya and {Al Sindi}, Nayef",
year = "2012",
doi = "10.1109/MWSCAS.2012.6292147",
language = "British English",
isbn = "9781467325264",
series = "Midwest Symposium on Circuits and Systems",
pages = "822--827",
booktitle = "2012 IEEE 55th International Midwest Symposium on Circuits and Systems, MWSCAS 2012",
note = "2012 IEEE 55th International Midwest Symposium on Circuits and Systems, MWSCAS 2012 ; Conference date: 05-08-2012 Through 08-08-2012",
}