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TDTL architecture with fast error correction technique

  • Omar Al-Kharji Al-Ali
  • , Nader Anani
  • , P. Ponnapalli
  • , M. A. Al-Qutayri
  • , S. R. Al-Araji

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

1 Scopus citations

Abstract

A new technique for fast error correction of the TDTL (time delay digital tanlock loop) is proposed. The technique is based on early comparison of the input signal frequency with that of the loop filter output. The result of this comparison is then used to select an optimum value for the loop filter output. This technique eliminates the need for continuously changing the loop filter coefficient. The major advantages of the proposed technique are a reduction in the complexity of the adaptive TDTL structure and an improvement in the loop acquisition time. The performance of the proposed system was tested using an FSK input signal and the results indicate enhanced performance compared to the conventional TDTL system.

Original languageBritish English
Title of host publication2010 IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2010 - Proceedings
Pages475-478
Number of pages4
DOIs
StatePublished - 2010
Event2010 IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2010 - Athens, Greece
Duration: 12 Dec 201015 Dec 2010

Publication series

Name2010 IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2010 - Proceedings

Conference

Conference2010 IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2010
Country/TerritoryGreece
CityAthens
Period12/12/1015/12/10

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