Systematic development of architectures for multidimensional DSP using the Residue Number System

D. Soudris, V. Paliouras, T. Stouraitis

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

In this paper a systematic methodology for mapping multidimensional algorithms onto array processor architectures based on the Quadratic Residue Number System is presented. We deal with a class of algorithms with separable functions, which can be reduced to the computation of the circular convolution. The array architecture results systematically from a directed graph using partitioning techniques and consists of identical processing elements called Inner Product Step Processors. Moreover, due to various graph partitions, many alternative array architectures in terms of I/O constraints, throughput, and hardware complexity, can be derived.

Original languageBritish English
Title of host publicationICASSP 1992 - 1992 International Conference on Acoustics, Speech, and Signal Processing
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages397-400
Number of pages4
ISBN (Electronic)0780305329
DOIs
StatePublished - 1992
Event1992 IEEE International Conference on Acoustics, Speech, and Signal Processing, ICASSP 1992 - San Francisco, United States
Duration: 23 Mar 199226 Mar 1992

Publication series

NameICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing - Proceedings
Volume3
ISSN (Print)1520-6149

Conference

Conference1992 IEEE International Conference on Acoustics, Speech, and Signal Processing, ICASSP 1992
Country/TerritoryUnited States
CitySan Francisco
Period23/03/9226/03/92

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