SR latch: The wrong introduction to digital memory

For over 60 years, textbooks on digital logic design have followed a semi-unified way to introduce the concept of digital memory. This method starts from a simple gate-based SR latch and applies several rectifications on it to obtain the D flip-flop. This method seems to have been influenced by the historical evolution of the SR latch from its relay-based variant in the 19th century, through its vacuum-tube version, to the transistor-based implementation. I argue that introducing the digital memory using this approach is problematic for learning as it implies several technical and pedagogical issues. This paper highlights these issues and proposes an alternative method which is based on an intuitive specification of the memory concept and a careful reasoning of related ideas including edge-sensitivity, synchronization, and the clock. I recommend adopting this method in textbooks and other learning resources.