TY - GEN
T1 - Single-clock-cycle, multilayer encryption algorithm for single-channel IoT communications
AU - Muzaffar, Shahzad
AU - Waheed, Owais Talaat
AU - Aung, Zeyar
AU - Elfadel, Ibrahim Abe M.
N1 - Funding Information:
VII. ACKNOWLEDGMENT This work has been supported by the Semiconductor Research Corporation (SRC) under the Abu Dhabi-SRC Center of Excellence on Energy-Efficient Electronic Systems (ACE4S), Contract 2013 HJ2440, with funding from the Mubadala Development Company, Abu Dhabi, UAE.
Publisher Copyright:
© 2017 IEEE.
PY - 2017/10/18
Y1 - 2017/10/18
N2 - Pulsed-Index Communication (PIC) is a novel technique for single-channel, high-data rate, low-power dynamic signaling that does not require any clock and data recovery. It is fully adapted to the simple yet robust communication needs of Internet of Things (IoT) devices and sensors. However, securing PIC using available conventional symmetric block cipher techniques is not feasible as it significantly degrades PIC attributes of low power, small area, and high data rates. For instance, symmetric stream ciphers such as A5/1 need several clock cycles to encrypt the data, which would reduce the PIC data rate. In this paper, we present a modified A5/1 cipher technique, called MA5/1, that generates a full keystream in one clock cycle, this securing PIC while satisfying all its requirements. Furthermore, using PIC's salient feature of transmitting index pulse streams, we provide an additional layer of packet security that makes it difficult for an attacker to receive and decode the packet before targeting MA5/1. When combined, these two techniques present a two-layer, hard-to-break challenge to an attacker, thus protecting PIC communication in an IoT network. The secure PIC is prototyped and verified in both FPGA and ASIC. In particular, we show that for an ASIC implementation in 65nm technology, the low-power operation of PIC is maintained, consuming only 27μW of power at a clock frequency of 25MHz.
AB - Pulsed-Index Communication (PIC) is a novel technique for single-channel, high-data rate, low-power dynamic signaling that does not require any clock and data recovery. It is fully adapted to the simple yet robust communication needs of Internet of Things (IoT) devices and sensors. However, securing PIC using available conventional symmetric block cipher techniques is not feasible as it significantly degrades PIC attributes of low power, small area, and high data rates. For instance, symmetric stream ciphers such as A5/1 need several clock cycles to encrypt the data, which would reduce the PIC data rate. In this paper, we present a modified A5/1 cipher technique, called MA5/1, that generates a full keystream in one clock cycle, this securing PIC while satisfying all its requirements. Furthermore, using PIC's salient feature of transmitting index pulse streams, we provide an additional layer of packet security that makes it difficult for an attacker to receive and decode the packet before targeting MA5/1. When combined, these two techniques present a two-layer, hard-to-break challenge to an attacker, thus protecting PIC communication in an IoT network. The secure PIC is prototyped and verified in both FPGA and ASIC. In particular, we show that for an ASIC implementation in 65nm technology, the low-power operation of PIC is maintained, consuming only 27μW of power at a clock frequency of 25MHz.
UR - http://www.scopus.com/inward/record.url?scp=85039909199&partnerID=8YFLogxK
U2 - 10.1109/DESEC.2017.8073841
DO - 10.1109/DESEC.2017.8073841
M3 - Conference contribution
AN - SCOPUS:85039909199
T3 - 2017 IEEE Conference on Dependable and Secure Computing
SP - 153
EP - 158
BT - 2017 IEEE Conference on Dependable and Secure Computing
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2017 IEEE Conference on Dependable and Secure Computing
Y2 - 7 August 2017 through 10 August 2017
ER -