Si nanowire memory

Ayman Rizk, Ammar Nayfeh

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

A novel Si nanowire memory cell is demonstrated by Physics Based TCAD simulation. The device utilizes the metal gate work function and the applied gate voltage to create potential barriers that trigger a positive feedback effect. Remarkably low voltage memory operation 1V is achieved with extremely long retention times (19.5s). The device is based on current high-κ metal gate technology and can be fabricated using standard CMOS process integration.

Original languageBritish English
Title of host publication2012 12th IEEE International Conference on Nanotechnology, NANO 2012
DOIs
StatePublished - 2012
Event2012 12th IEEE International Conference on Nanotechnology, NANO 2012 - Birmingham, United Kingdom
Duration: 20 Aug 201223 Aug 2012

Publication series

NameProceedings of the IEEE Conference on Nanotechnology
ISSN (Print)1944-9399
ISSN (Electronic)1944-9380

Conference

Conference2012 12th IEEE International Conference on Nanotechnology, NANO 2012
Country/TerritoryUnited Kingdom
CityBirmingham
Period20/08/1223/08/12

Keywords

  • Memory
  • Nanowire
  • Retention

Fingerprint

Dive into the research topics of 'Si nanowire memory'. Together they form a unique fingerprint.

Cite this