TY - GEN
T1 - Seventeen Level Switch Capacitor-Based Cascaded Multilevel Inverter with Low Device Count
AU - Baksi, Swapan Kumar
AU - Behera, Ranjan Kumar
AU - Al Jaafari, Khaled
AU - Al Hosani, Khalifa
AU - Muduli, Utkal Ranjan
N1 - Publisher Copyright:
© 2023 IEEE.
PY - 2023
Y1 - 2023
N2 - This paper proposes a novel cascaded multilevel inverter (CMLI) structure based on switch capacitor (SC) tech-nology, which is capable of achieving up to 17 levels. The inverter is constructed by cascading two SC-based 9-level MLI basic modules, resulting in a 17-level SC-CMLI structure. The proposed inverter employs a reduced number of power switches, floating capacitors, gate drives, and dc sources, making it easy to implement. The Nearest level Control PWM technique is used to generate the switching pulses for the proposed 17-level CMLI. The proposed inverter is simulated under different modulation indices and dynamic load change conditions. The output voltage waveforms have significantly less total harmonic distortion (THD) content of 5.18%. The theoretical analysis of the proposed inverter is verified using MATLAB/Simulink software. Overall, the results demonstrate that the proposed 17-level SC-CMLI is an efficient and practical solution for high-power applications. This topology can be extended to higher voltage levels.
AB - This paper proposes a novel cascaded multilevel inverter (CMLI) structure based on switch capacitor (SC) tech-nology, which is capable of achieving up to 17 levels. The inverter is constructed by cascading two SC-based 9-level MLI basic modules, resulting in a 17-level SC-CMLI structure. The proposed inverter employs a reduced number of power switches, floating capacitors, gate drives, and dc sources, making it easy to implement. The Nearest level Control PWM technique is used to generate the switching pulses for the proposed 17-level CMLI. The proposed inverter is simulated under different modulation indices and dynamic load change conditions. The output voltage waveforms have significantly less total harmonic distortion (THD) content of 5.18%. The theoretical analysis of the proposed inverter is verified using MATLAB/Simulink software. Overall, the results demonstrate that the proposed 17-level SC-CMLI is an efficient and practical solution for high-power applications. This topology can be extended to higher voltage levels.
KW - Cascade Multilevel Inverter
KW - Device count
KW - Nearest level control
KW - pulse width modulation (PWM)
KW - Switch capacitor
KW - Total harmonic distortion
UR - http://www.scopus.com/inward/record.url?scp=85179521291&partnerID=8YFLogxK
U2 - 10.1109/IECON51785.2023.10312153
DO - 10.1109/IECON51785.2023.10312153
M3 - Conference contribution
AN - SCOPUS:85179521291
T3 - IECON Proceedings (Industrial Electronics Conference)
BT - IECON 2023 - 49th Annual Conference of the IEEE Industrial Electronics Society
PB - IEEE Computer Society
T2 - 49th Annual Conference of the IEEE Industrial Electronics Society, IECON 2023
Y2 - 16 October 2023 through 19 October 2023
ER -