Second-order TDTL with initialization process

M. A. Al-Qutayri, S. R. Al-Araji, J. Jeedella, O. A.K. Al-Ali, N. A. Anani

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

1 Scopus citations

Abstract

This paper proposes an improved time delay digital tanlock loop (TDTL) system in which a feedforward loop is used to initialize the loop filter memory so as to enhance the acquisition speed of the system. The feedforward loop is used to estimate the value of the steady-state frequency of the input signal which is subsequently loaded into the memory of the loop filter. The system was simulated and tested using Simulink/Matalb using frequency step and FSK modulation. Further, the system was implemented using an FPGA and testing results indicate an ample improvement in the acquisition speed over the original TDTL system.

Original languageBritish English
Title of host publication2012 19th IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2012
Pages909-912
Number of pages4
DOIs
StatePublished - 2012
Event2012 19th IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2012 - Seville, Seville, Spain
Duration: 9 Dec 201212 Dec 2012

Publication series

Name2012 19th IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2012

Conference

Conference2012 19th IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2012
Country/TerritorySpain
CitySeville, Seville
Period9/12/1212/12/12

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