@inproceedings{c1c3eac8741d46429d97cabf663aeb46,
title = "Second order TDTL performance analysis and FPGA implementation",
abstract = "This paper presents the architecture, and the mathematical and simulation models of the second order time delay tanlock loop (TDTL). It discusses the transformation of the loop blocks and their subsequent implementation on an FPGA prototype system. The real time results of the FPGA based TDTL system are in agreement with those obtained from simulation. Compared with the first order, the response of the second order loop converges to zero but with a restricted locking range.",
author = "Mahmoud Al-Qutayri and Saleh Al-Araji and Nawaf Al-Moosa",
year = "2006",
language = "British English",
isbn = "1424400872",
series = "Proceedings of the Mediterranean Electrotechnical Conference - MELECON",
pages = "514--517",
booktitle = "2006 IEEE Mediterranean Electrotechnical Conference, MELECON 2006 - Circuits and Systems for Signal Processing, lnformation and Communication Technologies, and Power Sources and Systems",
note = "2006 IEEE Mediterranean Electrotechnical Conference, MELECON 2006 ; Conference date: 16-05-2006 Through 19-05-2006",
}