TY - GEN
T1 - Second-order single channel digital tanlock based phase-locked loop
AU - Al-Ali, Omar Al Kharji
AU - Anani, Nader
AU - Al-Qutayri, Mahmoud
AU - Al-Araji, Saleh
AU - Ponnapalli, Prasad
PY - 2012
Y1 - 2012
N2 - The design of a second-order digital phase-locked loop (DPLL) based on the time-delay digital tanlock loop (TDTL) architecture is presented. The proposed design simplifies the architecture of the TDTL by eliminating the requirement for the time delay block. In addition, the system includes a controller block whose output feeds into the arctan phase detector of the proposed system so as to optimize the acquisition time and/or the lock range of the loop. The system performance evaluation results show that it is possible to selectively optimize certain parameters of the system in order to match specific application requirements.
AB - The design of a second-order digital phase-locked loop (DPLL) based on the time-delay digital tanlock loop (TDTL) architecture is presented. The proposed design simplifies the architecture of the TDTL by eliminating the requirement for the time delay block. In addition, the system includes a controller block whose output feeds into the arctan phase detector of the proposed system so as to optimize the acquisition time and/or the lock range of the loop. The system performance evaluation results show that it is possible to selectively optimize certain parameters of the system in order to match specific application requirements.
UR - http://www.scopus.com/inward/record.url?scp=84868579931&partnerID=8YFLogxK
U2 - 10.1109/CSNDSP.2012.6292685
DO - 10.1109/CSNDSP.2012.6292685
M3 - Conference contribution
AN - SCOPUS:84868579931
SN - 9781457714733
T3 - Proceedings of the 2012 8th International Symposium on Communication Systems, Networks and Digital Signal Processing, CSNDSP 2012
BT - Proceedings of the 2012 8th International Symposium on Communication Systems, Networks and Digital Signal Processing, CSNDSP 2012
T2 - 2012 8th International Symposium on Communication Systems, Networks and Digital Signal Processing, CSNDSP 2012
Y2 - 18 July 2012 through 20 July 2012
ER -