Second-order single channel digital tanlock based phase-locked loop

Omar Al Kharji Al-Ali, Nader Anani, Mahmoud Al-Qutayri, Saleh Al-Araji, Prasad Ponnapalli

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

The design of a second-order digital phase-locked loop (DPLL) based on the time-delay digital tanlock loop (TDTL) architecture is presented. The proposed design simplifies the architecture of the TDTL by eliminating the requirement for the time delay block. In addition, the system includes a controller block whose output feeds into the arctan phase detector of the proposed system so as to optimize the acquisition time and/or the lock range of the loop. The system performance evaluation results show that it is possible to selectively optimize certain parameters of the system in order to match specific application requirements.

Original languageBritish English
Title of host publicationProceedings of the 2012 8th International Symposium on Communication Systems, Networks and Digital Signal Processing, CSNDSP 2012
DOIs
StatePublished - 2012
Event2012 8th International Symposium on Communication Systems, Networks and Digital Signal Processing, CSNDSP 2012 - Poznan, Poland
Duration: 18 Jul 201220 Jul 2012

Publication series

NameProceedings of the 2012 8th International Symposium on Communication Systems, Networks and Digital Signal Processing, CSNDSP 2012

Conference

Conference2012 8th International Symposium on Communication Systems, Networks and Digital Signal Processing, CSNDSP 2012
Country/TerritoryPoland
CityPoznan
Period18/07/1220/07/12

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