RECONFIGURABLE SYSTOLIC PRIMITIVE PROCESSOR FOR SIGNAL PROCESSING.

T. Stouraitis, S. Natarajan, F. J. Taylor

Research output: Contribution to journalConference articlepeer-review

2 Scopus citations

Abstract

To overcome the 12-bit historical address space limit of high-speed lookup memory devices, a new adaptive radix processor (ARP) is proposed, and an error analysis is performed. Interconnecting a number of identical ARPs, fast and compact digital signal processing systems can be designed operating on a low error budget over a large dynamic range. Examples are presented using a shared memory design. Finally, due to identical processors used in the designs, reconfiguration can be used to fully utilize the available hardware and/or introduce a degree of fault tolerance.

Original languageBritish English
Pages (from-to)280-283
Number of pages4
JournalICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing - Proceedings
StatePublished - 1985

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