Reconfigurable systolic array for polynomial multiplication modulo Xn±1

Zarir Sarkari; Alexander Skavantzos; Thanos Stouraitis

Reconfigurable systolic array for polynomial multiplication modulo Xⁿ±1

Zarir Sarkari, Alexander Skavantzos, Thanos Stouraitis

Electrical Engineering

Louisiana State University

Research output: Contribution to conference › Paper › peer-review

Abstract

A simple reconfigurable processor array that utilizes the polynomial residue number system (PRNS) for polynomial multiplication is presented. The mesh-connected systolic array is, in fact, a combination of linear one-dimensional arrays operating in parallel. The reconfiguration scheme is based on a dual role played by the processing elements constituting the array.

Original language	British English
Pages	460-464
Number of pages	5
State	Published - Mar 1989
Event	Proceedings: the Twenty-First Southeastern Symposium on System Theory - Tallahassee, FL, USA Duration: 26 Mar 1989 → 28 Mar 1989

Conference

Conference	Proceedings: the Twenty-First Southeastern Symposium on System Theory
City	Tallahassee, FL, USA
Period	26/03/89 → 28/03/89

Cite this

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title = "Reconfigurable systolic array for polynomial multiplication modulo Xn±1",

abstract = "A simple reconfigurable processor array that utilizes the polynomial residue number system (PRNS) for polynomial multiplication is presented. The mesh-connected systolic array is, in fact, a combination of linear one-dimensional arrays operating in parallel. The reconfiguration scheme is based on a dual role played by the processing elements constituting the array.",

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AU - Skavantzos, Alexander

AU - Stouraitis, Thanos

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N2 - A simple reconfigurable processor array that utilizes the polynomial residue number system (PRNS) for polynomial multiplication is presented. The mesh-connected systolic array is, in fact, a combination of linear one-dimensional arrays operating in parallel. The reconfiguration scheme is based on a dual role played by the processing elements constituting the array.

AB - A simple reconfigurable processor array that utilizes the polynomial residue number system (PRNS) for polynomial multiplication is presented. The mesh-connected systolic array is, in fact, a combination of linear one-dimensional arrays operating in parallel. The reconfiguration scheme is based on a dual role played by the processing elements constituting the array.

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M3 - Paper

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T2 - Proceedings: the Twenty-First Southeastern Symposium on System Theory

Y2 - 26 March 1989 through 28 March 1989

ER -

Reconfigurable systolic array for polynomial multiplication modulo Xⁿ±1

Abstract

Conference

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