Processor-memory interconnection issues for multiprocessor systems

Hao po Chan, Thanos Stouraitis

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

A systematic method for analyzing the performance of processor-memory interconnection networks is presented. This method is applicable under the assumption that the whole memory system can be partitioned into several groups, with each group containing memory modules of the same type. This is called the common favorite memory condition. The performance of the augmented baseline interconnection networks under this condition is analyzed. A novel interconnection network featuring simpler hardware and fewer gate delays is presented and compared to the baseline interconnection networks.

Original languageBritish English
Title of host publicationConference Record - Asilomar Conference on Circuits, Systems & Computers
EditorsRay R. Chen
Pages12-16
Number of pages5
StatePublished - 1989
EventTwenty-Third Annual Asilomar Conference on Signals, Systems & Computers - Pacific Grove, CA, USA
Duration: 30 Oct 19891 Nov 1989

Publication series

NameConference Record - Asilomar Conference on Circuits, Systems & Computers
Volume1
ISSN (Print)0736-5861

Conference

ConferenceTwenty-Third Annual Asilomar Conference on Signals, Systems & Computers
CityPacific Grove, CA, USA
Period30/10/891/11/89

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