TY - GEN
T1 - Performance Analysis of A Switched-Capacitor Based 13-Level Boost Cascaded Multilevel Inverter With Reduced Device Count
AU - Baksi, Swapan Kumar
AU - Behera, Ranjan Kumar
AU - Jaafari, Khaled Al
AU - Hosani, Khalifa Al
AU - Muduli, Utkal Ranjan
N1 - Publisher Copyright:
© 2023 IEEE.
PY - 2023
Y1 - 2023
N2 - This paper introduces a cascaded 13-level multilevel inverter (MLI) based on switch capacitor (SC) technology, which inherently boosts voltage. The architecture is formed by connecting two 7-level SC-based boost MLI basic modules to create a 13-level SCMLI. Each of these 7-level modules is comprised of eight power switches, one floating capacitor, two dc- link capacitors, and a single dc source. The design of the 13-level MLI minimizes the requirement for power switches, gate drivers, floating capacitors, and dc sources. Switching pulses for this 13- level MLI are generated using the Nearest-level Pulse Width Modulation (PWM) technique. Simulation of the inverter under varying modulation indices and dynamic load conditions reveals a total harmonic distortion (THD) of just 6.58% in the output voltage. This THD measurement covers a modulation index range from 0.1 to 1. Validation of the theoretical framework is carried out through MATLAB/Simulink simulations, and comparisons are drawn considering the count of power switches, capacitors, gate drivers, and dc sources.
AB - This paper introduces a cascaded 13-level multilevel inverter (MLI) based on switch capacitor (SC) technology, which inherently boosts voltage. The architecture is formed by connecting two 7-level SC-based boost MLI basic modules to create a 13-level SCMLI. Each of these 7-level modules is comprised of eight power switches, one floating capacitor, two dc- link capacitors, and a single dc source. The design of the 13-level MLI minimizes the requirement for power switches, gate drivers, floating capacitors, and dc sources. Switching pulses for this 13- level MLI are generated using the Nearest-level Pulse Width Modulation (PWM) technique. Simulation of the inverter under varying modulation indices and dynamic load conditions reveals a total harmonic distortion (THD) of just 6.58% in the output voltage. This THD measurement covers a modulation index range from 0.1 to 1. Validation of the theoretical framework is carried out through MATLAB/Simulink simulations, and comparisons are drawn considering the count of power switches, capacitors, gate drivers, and dc sources.
KW - cascaded multilevel inverter
KW - Nearest level PWM
KW - Reduce switch count
KW - Switch capacitors
KW - Total harmonic distortion
UR - https://www.scopus.com/pages/publications/85186501908
U2 - 10.1109/STPEC59253.2023.10430685
DO - 10.1109/STPEC59253.2023.10430685
M3 - Conference contribution
AN - SCOPUS:85186501908
T3 - 2023 IEEE 3rd International Conference on Smart Technologies for Power, Energy and Control, STPEC 2023
BT - 2023 IEEE 3rd International Conference on Smart Technologies for Power, Energy and Control, STPEC 2023
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 3rd IEEE International Conference on Smart Technologies for Power, Energy and Control, STPEC 2023
Y2 - 10 December 2023 through 13 December 2023
ER -