Parallelised max-Log-Map model

K. K. Loo, K. Salman, T. Alukaidey, S. A. Jimaa

Research output: Contribution to journalArticlepeer-review

3 Scopus citations

Abstract

A parallelised max-Log-MAP model (P-max-Log-MAP) that exploits the sub-word parallelism and very long instruction word architecture of a microprocessor or a digital signal processor (DSP) is presented. The proposed model reduces considerably the computational complexity of the max-Log-MAP algorithm; and therefore facilitates easy implementation.

Original languageBritish English
Pages (from-to)971-972
Number of pages2
JournalElectronics Letters
Volume38
Issue number17
DOIs
StatePublished - 15 Aug 2002

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