Parallelised max-Log-Map model

K. K. Loo; K. Salman; T. Alukaidey; S. A. Jimaa

doi:10.1049/el:20020663

Parallelised max-Log-Map model

K. K. Loo, K. Salman, T. Alukaidey, S. A. Jimaa

Electrical Engineering

University of Hertfordshire

Research output: Contribution to journal › Article › peer-review

3 Scopus citations

Abstract

A parallelised max-Log-MAP model (P-max-Log-MAP) that exploits the sub-word parallelism and very long instruction word architecture of a microprocessor or a digital signal processor (DSP) is presented. The proposed model reduces considerably the computational complexity of the max-Log-MAP algorithm; and therefore facilitates easy implementation.

Original language	British English
Pages (from-to)	971-972
Number of pages	2
Journal	Electronics Letters
Volume	38
Issue number	17
DOIs	https://doi.org/10.1049/el:20020663
State	Published - 15 Aug 2002

Access to Document

10.1049/el:20020663

Cite this

@article{cd5de10850584cc6b790c601166a4ec3,

title = "Parallelised max-Log-Map model",

abstract = "A parallelised max-Log-MAP model (P-max-Log-MAP) that exploits the sub-word parallelism and very long instruction word architecture of a microprocessor or a digital signal processor (DSP) is presented. The proposed model reduces considerably the computational complexity of the max-Log-MAP algorithm; and therefore facilitates easy implementation.",

author = "Loo, {K. K.} and K. Salman and T. Alukaidey and Jimaa, {S. A.}",

year = "2002",

month = aug,

day = "15",

doi = "10.1049/el:20020663",

language = "British English",

volume = "38",

pages = "971--972",

journal = "Electronics Letters",

issn = "0013-5194",

publisher = "John Wiley & Sons Inc.",

number = "17",

}

TY - JOUR

T1 - Parallelised max-Log-Map model

AU - Loo, K. K.

AU - Salman, K.

AU - Alukaidey, T.

AU - Jimaa, S. A.

PY - 2002/8/15

Y1 - 2002/8/15

N2 - A parallelised max-Log-MAP model (P-max-Log-MAP) that exploits the sub-word parallelism and very long instruction word architecture of a microprocessor or a digital signal processor (DSP) is presented. The proposed model reduces considerably the computational complexity of the max-Log-MAP algorithm; and therefore facilitates easy implementation.

AB - A parallelised max-Log-MAP model (P-max-Log-MAP) that exploits the sub-word parallelism and very long instruction word architecture of a microprocessor or a digital signal processor (DSP) is presented. The proposed model reduces considerably the computational complexity of the max-Log-MAP algorithm; and therefore facilitates easy implementation.

UR - http://www.scopus.com/inward/record.url?scp=0037102025&partnerID=8YFLogxK

U2 - 10.1049/el:20020663

DO - 10.1049/el:20020663

M3 - Article

AN - SCOPUS:0037102025

SN - 0013-5194

VL - 38

SP - 971

EP - 972

JO - Electronics Letters

JF - Electronics Letters

IS - 17

ER -

Parallelised max-Log-Map model

Abstract

Access to Document

Other files and links

Fingerprint

Cite this