Abstract
The authors discuss the mathematical basis and hardware implementations of new complex multipliers. They are based on appropriate encoding of complex numbers as polynomials and on a recently developed arithmetic system, the polynomial residue number system (PRNS), in which totally parallel polynomial multiplication can be achieved provided that the arithmetic takes place in some carefully chosen ring. A no-error third-order and a small-error seventh-order polynomial encoding are examined. The new multipliers allow a variety of implementation options and are shown to exhibit performance up to 3.5 times better than traditional techniques in a multiplicative intensive environment.
| Original language | British English |
|---|---|
| Pages (from-to) | 379-383 |
| Number of pages | 5 |
| Journal | Conference Record - Asilomar Conference on Circuits, Systems & Computers |
| Volume | 1 |
| State | Published - 1988 |
| Event | v 1 (of 2) - Pacific Grove, CA, USA Duration: 31 Oct 1988 → 2 Nov 1988 |