On using a new Dynamic Reconfigurable Logic (DRL) VLSI circuit for very high speed routing

Research output: Contribution to journalConference articlepeer-review

Abstract

Recent efforts to add new services to the Internet have increased the interest in designing flexible routers that are easy to extend and evolve. This paper describes a new hardware architecture based on Dynamic Reconfigurable Logic (DRL) for high throughput networking applications. It mainly focuses on content-based router and on how to schedule efficiently its computation time. This scheduling task is difficult because of the various features of the underlying hardware such as multicontext, control-data path architecture and memory interface. Experimental results show some improvements over most recent network processors as well as a better hardware synthesis methodology.

Original languageBritish English
Pages (from-to)830-833
Number of pages4
JournalIEEE International Conference on Communications
Volume2
StatePublished - 2003
Event2003 International Conference on Communications (ICC 2003) - Anchorage, AK, United States
Duration: 11 May 200315 May 2003

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