TY - GEN
T1 - On the intrinsic complexity of logical transformation problems
AU - Shoufan, Abdulhadi
AU - Alnaqbi, Abdulla
N1 - Funding Information:
This work was supported by the Center for Teaching and Learning at Khalifa University. Thanks to all students who took DLD in Spring 2017 and did their best to provide solving data for this research.
Publisher Copyright:
© 2018 IEEE.
PY - 2018/5/23
Y1 - 2018/5/23
N2 - The design of combinatorial and sequential circuits relies on multiple logical transformations that can show different levels of complexity. This paper investigates the intrinsic complexity of eight logical transformation problems: (1)-from human-language statement into formal function, (2)-from formal function into truth table, (3)-from truth table into formal function, (4)-from formal function into k-map, (5)-from truth table into k-map, (6)-from k-map into minimized formal function, (7)-from formal function into minimized formal function using Boolean algebra, and (8)-from formal function into digital circuit. 27 potential complexity variables were first identified and specified and a total of 303 test items/problems were generated and solved by up to 43 students each with time recording. The level of intrinsic complexity was defined based on average solving time and error ratio. Regression models were generated to establish a predictive relationship between the intrinsic complexity level and the complexity variables for each transformation problem. Apart from Transformation 7, the regression models showed adjusted R-square values between 81% and 94%. These models can be used to predict the solving time of new problems towards more reliable test design.
AB - The design of combinatorial and sequential circuits relies on multiple logical transformations that can show different levels of complexity. This paper investigates the intrinsic complexity of eight logical transformation problems: (1)-from human-language statement into formal function, (2)-from formal function into truth table, (3)-from truth table into formal function, (4)-from formal function into k-map, (5)-from truth table into k-map, (6)-from k-map into minimized formal function, (7)-from formal function into minimized formal function using Boolean algebra, and (8)-from formal function into digital circuit. 27 potential complexity variables were first identified and specified and a total of 303 test items/problems were generated and solved by up to 43 students each with time recording. The level of intrinsic complexity was defined based on average solving time and error ratio. Regression models were generated to establish a predictive relationship between the intrinsic complexity level and the complexity variables for each transformation problem. Apart from Transformation 7, the regression models showed adjusted R-square values between 81% and 94%. These models can be used to predict the solving time of new problems towards more reliable test design.
KW - digital logic design
KW - Intrinsic complexity
KW - problem solving time
KW - regression models
UR - http://www.scopus.com/inward/record.url?scp=85048097041&partnerID=8YFLogxK
U2 - 10.1109/EDUCON.2018.8363282
DO - 10.1109/EDUCON.2018.8363282
M3 - Conference contribution
AN - SCOPUS:85048097041
T3 - IEEE Global Engineering Education Conference, EDUCON
SP - 577
EP - 584
BT - Proceedings of 2018 IEEE Global Engineering Education Conference
PB - IEEE Computer Society
T2 - 2018 IEEE Global Engineering Education Conference - Emerging Trends and Challenges of Engineering Education, EDUCON 2018
Y2 - 17 April 2018 through 20 April 2018
ER -