Obtaining Performance of Type-3 Phase-Locked Loop Without Compromising the Benefits of Type-2 Control System

A phase-locked loop (PLL) is a closed-loop feedback control system that estimates the frequency as well as phase of an input signal. The most commonly deployed synchronization method in three-phase applications is a type-2 synchronous reference frame PLL. With pre/in-loop selective harmonic filtering stage, type-2 PLLs can obtain good detection speed, decent stability margins, and better disturbance rejection. However, it suffers from the finite steady-state phase error during ramp change in input signal frequency. To tackle this challenge type-3 PLLs have been developed recently, either by adding a feed-forward path to the PLL structure, or by using a second-order controller as the loop filter. However, recent analysis carried out of type-3 PLLs show that they aggravate stability problem and compromise the performance in terms of detection speed and disturbance rejection. A new concept of synchronization is proposed in this paper that obtains the performance of type-3 PLL but retains all the advantages associated with type-2 PLL. Extensive experimental results are provided to validate the proposed work.